Output Reflection Coefficients Research Articles

DESIGN AND SIMULATION OF S-BAND MICROWAVE AMPLIFIER FOR SATELLITE COMMUNICATIONS SYSTEM

This paper presents a novel design of S-band monolithic microwave integrated circuit (MMIC) amplifiers based on GaAs MESFET HFET-1102 transistors used in radiofrequency (RF) and microwave communications systems. Based on the Chebyshev gain response, an analytical method is used to design a two-stage lumped microwave amplifier. The matching networks constituted by lumped elements are transformed into T inductive networks, and the resulting amplifier is optimized using RF simulator software. In the following step, the lumped optimized amplifier is transformed into a distributed amplifier and implemented on Rogers TMM3 substrate largely used in microwave circuits. The final MMIC amplifier is stable in the frequency band (2-4 GHz), and excellent performances are obtained in terms of very high gain, reaching a peak of 35 dB, low input (S11) and output reflection (S22) coefficients, and very good output/input isolation (S12). For its RF characteristics, the proposed MMIC amplifier presented in this work is very suitable for space telecommunications in low earth orbit (LEO) satellites onboard receivers.

Design and fabrication of S-band power amplifier for wireless sensor networks

This paper discusses the process of designing and manufacturing a wideband power amplifier operating in the S-band. To amplify a low power and broadband radio frequency signals from 2.1 GHz to 2.5 GHz, the proposed power amplifier uses a diagram of a two-stages amplification with peak offset amplification frequency 2.3 GHz. The power amplifier is designed with a center frequency difference of 2.2 GHz and 2.4 GHz respectively to achieve a bandwidth of 400 MHz. The proposed power amplifier (PA) uses RF transistor SHF-0589 using gallium arsenide heterostructure field-effect transistor (GaAs HFET) technology for high gain and low power consumption. The complete amplifier achieves power gain 21.1 dB inband 2.1-2.5 GHz and achieve maximum power gain of 22.5 dB at the frequency of 2.4 GHz; the output power rise up to 33 dBm; input reflection coefficient (S11) reaches -19.2 dB and output reflection coefficient reaches -17.2 dB. The designed amplifier circuit can be used for wireless sensor networks operating at S-band.

Design of a low power LNA circuit with noise canceling approach in 90 nm CMOS process

In this manuscript, a low noise amplifier (LNA) circuit with low power consumption of 5.3 mW for 3–12 GHz ultra-wideband (UWB) is designed in 90 nm standard CMOS process. A noise-canceling (NC) approach consisting of both common-gate (CG) and common-source (CS) as input stage, followed by the gm-boosted current-reused stage to enhance the gain performance, is used in the proposed design. After noise-canceling, the achieved noise-figure (NF) is ranging from 2.28 to 3.55 dB for 3.1–10.6 GHz and a maximum of 4.0 dB at 12 GHz. Input-reflection coefficient (S11) of < −12.57 dB is achieved from this CG-CS input-matching stage. With the use of parallel-series LC matching with series-peaking-inductor followed by the gm-boosting stage improves the gain-bandwidth and delivers a flat power-gain (S21) of 18.33 ± 0.76 dB over 3–12 GHz. The CG configuration at the input side provides a high reverse-isolation (S12) of less than −78.23 dB and common-drain configuration with NMOS load at the output side ensures less than −11.79 dB output-reflection coefficient (S22) over the proposed frequency range. The proposed LNA is operated with 0.7 V Vdd and the achieved intercept points for input (IIP3) and output (OIP3) are −11.1 dBm and +6.2 dBm, respectively.

Design and optimization of variable gain LNA for IoT applications using meta-heuristics search algorithms

In this paper, Variable Gain LNA (VG-LNA) parameters are optimized using the Particle Swarm Optimization (PSO), Firefly Algorithm (FA), and Genetic Algorithm (GA). A comparison of the three optimization techniques has been done and FA is depicting better results over GA and PSO. VG-LNA is composed of a Complementary Common Gate (CCG) and Variable Gain Amplifier (VGA). Gm-boost topology helps in increasing the gain while the current reuse technique provides less power consumption. Optimization algorithms simulated on MATLAB and the result shows minimum Noise Fig. (NF) is 2.62 dB, maximum gain is 17.8 dB, S11 i.e. input reflection coefficient is −13.5 dB and S22 i.e. output reflection coefficient is −14.7 dB at 50 Ω impedance matching while Figure of Merit1 (FoM1) is 36.14 dB using FA. The FA optimized parameters when simulated on Cadence Virtuoso software using GPDK 45 nm CMOS technology for the frequency range of 26–32 GHz then results show a minimum NF of 2.6 dB at 30.9 GHz, maximum gain of 16.9 dB at 30.5 GHz, S11 is −17.7 dB at 30.5 GHz, S22 is −21.2 dB at 29 GHz and FoM1 of 34.19 dB. The layout of the realized circuit has an area of 231.695 μm*164.48 μm i.e. 0.03811mm2.

Design and Development of Compact Wilkinson Power Divider on Gallium Nitride Coplanar Technology

In this article, an ultra-compact monolithic microwave integrated Wilkinson power divider (WPD) was accomplished for X-band applications. So as to reduce the size of the design, the miniaturization technique was illustrated with the theoretical analysis. After the theoretical analysis, the layout of the design and electromagnetic simulation were performed. The proposed Wilkinson power divider was manufactured with utilizing gallium nitride integrated passive device technology. In the measurement results, it was seen that the input and output (I/O) reflection coefficients were better than -15 dB in the frequency bandwidth of 8-12 GHz. In addition, the insertion loss was measured less than -4 dB in the X-band (8-12 GHz). Moreover, the 15-dB fractional bandwidth is 40% and the isolation between the outputs are better than -15 dB. The size of the proposed Wilkinson power was reduced to the dimensions of 700 m  700 m (0.047 λg x 0.047 λg, where λg is the wavelength value at the center frequency (10 GHz)), as 𝜋-type miniaturization technique was employed with monolithic lumped components. Beside its miniaturized size, the proposed power divider exhibits broadband characteristics while having any degradation in the electrical performance.

Design of an ultra-wideband LNA using transformer matching method

A new transformer matching method for ultra-wideband (UWB) low noise amplifier is presented, which effectively extends the bandwidth and has little effect on the circuit noise. Low-frequency gain compression are realized by combining Frlan-style transformer and RC feedback loop topology in the interstage. The output matching network is composed of the Rabjohn-style transformer and LC network after Norton transformation. The power gain is enhanced by using two-stage cascode topology. The proposed UWB LNA is based on a 0.25um GaAs PHEMT process, and the post-layout simulation results show the maximum power gain of 21 dB, minimum NF of 1.6 dB in the frequency range of 4–15 GHz. The input reflection coefficient is less than -7dB. The output reflection coefficient is less than −10dB. The average output 1-dB compression point is 14dBm. The chip size is 0.82 mm2.

Design and robustness improvement of high‐performance LNA using 0.15 μm GaN technology for X‐band applications

SummaryIn this paper, we present a highly robust GaN‐based X‐band low‐noise amplifier (LNA) showing promising small‐signal and noise performance as well as good linearity. The LNA is fabricated using in‐house 0.15 μm AlGaN/GaN on a SiC HEMT process. Owing to the optimum choice of HEMT topologies and simultaneous matching technique, LNA achieves a noise figure better than 2 dB, output power at 1 dB gain compression higher than 19 dB, input and output reflection coefficients better than −9 and −11 dB, respectively. The small‐signal gain of LNA is more than 19 dB for the whole band, and NF has a minimum of 1.74 dB at 10.2 GHz. LNA obtains an OIP3 up to 34.2 dBm and survives input power as high as 42 dBm. Survivability is investigated in terms of gain compression and forward gate current. Reverse recovery time (RRT), a crucial parameter for radar front‐ends, is explored with respect to the RC time constant and trap phenomenon. The analysis shows that the significant contribution in RRT is due to traps while the RC time constant is in the nanoseconds range. Moreover, this study also addresses the requirement and choice of a DC gate feed resistor for the subsequent stages in a multi‐stage design. The size of the designed LNA chip is 3 mm 1.2 mm only.

A 20-44 GHz Wideband LNA Design Using the SiGe Technology for 5G Millimeter-Wave Applications.

This paper presents the design and implementation of a low-noise amplifier (LNA) for millimeter-wave (mm-Wave) 5G wireless applications. The LNA was based on a common-emitter configuration with cascode amplifier topology using an IHP’s 0.13 μm Silicon Germanium (SiGe) heterojunction bipolar transistor (HBT) whose f_T/f_MAX/gate-delay is 360/450 GHz/2.0 ps, utilizing transmission lines for simultaneous noise and input matching. A noise figure of 3.02–3.4 dB was obtained for the entire wide bandwidth from 20 to 44 GHz. The designed LNA exhibited a gain (S_21) greater than 20 dB across the 20–44 GHz frequency range and dissipated 9.6 mW power from a 1.2 V supply. The input reflection coefficient (S_11) and output reflection coefficient (S_22) were below −10 dB, and reverse isolation (S_12) was below −55 dB for the 20–44 GHz frequency band. The input 1 dB (P1dB) compression point of −18 dBm at 34.5 GHz was obtained. The proposed LNA occupies only a 0.715 mm2 area, with input and output RF (Radio Frequency) bond pads. To the authors’ knowledge, this work evidences the lowest noise figure, lowest power consumption with reasonable highest gain, and highest bandwidth attained so far at this frequency band in any silicon-based technology.

A Millimeter-Wave Mutual-Coupling-Resilient Double-Quadrature Transmitter for 5G Applications

This article presents a wideband energy-efficient transmitter (TX) for 5G mm-wave phased-array systems. It features an advanced double-quadrature direct upconverter (DQ-DUC) to improve its in-band linearity and spectral purity. The proposed TX architecture incorporates an efficiency-enhanced balanced power amplifier (EEBPA) that mitigates VSWR fluctuations in phased-array systems while enhancing efficiency at power back-off (PBO). The EEBPA comprises two identical series-Doherty power amplifiers (PAs) combined through a quadrature hybrid coupler forming a balanced PA. The proposed DQ-DUC consists of a pair of I/Q modulators and the proposed EEBPA’s quadrature combiner to further suppress the I/Q image. To verify the proposed techniques, a 40-nm CMOS prototype is implemented. It delivers 20 dBm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P~_{\text {1 dB}}$ </tex-math></inline-formula> with 40%/31% drain efficiency at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P~_{\text {1 dB}}$ </tex-math></inline-formula> /6-dB PBO. The measured TX output reflection coefficient is better than −18 dB over a 22.5–30-GHz band. Its intrinsic LO feedthrough and image-rejection ratio for a 100-MHz tone spacing over a 24–30-GHz band are better than −45 dBc/50 dB, respectively, without calibration. The average error vector magnitude (EVM) is better than −27.1 dB without digital pre-distortion for an eight-carrier “100-MHz 64-QAM OFDM” signal with an 800-MHz aggregated bandwidth while generating an average output power of 8.4 dBm with 10.8% drain efficiency. Its maximum forward-power/EVM deviations are better than 0.3/1.65 dB, respectively, for a “100-MHz 64-QAM” signal under a voltage standing wave ratio of 3.

Low Noise Amplifier with Improved Gain and Reduced Noise-Figure in 90nm CMOS Technology

A CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented in this paper. The proposed CMOS low noise amplifier (LNA) is designed using common-gate (CG) topology as the first stage to achieve ultra-wideband input matching. The common-gate (CG) is cascaded with common- source (CS) topology with current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power. The Buffer stage is used as output matching network to improve the reflection coefficient. The proposed low noise amplifier (LNA) is implemented using CADENCE Virtuoso Analog and Digital Design Environment tool in 90nm CMOS technology. The LNA provides a forward voltage gain or power gain (S21) of 32.34dB , a minimum noise figure of 2dB, a reverse-isolation (S12) of less than - 38.74dB and an output reflection coefficient (S22) of less than -7.4dB for the entire ultra-wideband frequency range. The proposed LNA has an input reflection coefficient (S11) of less than -10dB for the ultra-wideband frequency range. It achieves input referred 1-dB compression point of 78.53dBm and input referred 3-dB compression point of 13dBm. It consumes only 24.226mW of power from a Vdd supply of 0.7V.

Design of high power amplifier based on wilkinson power combiner for wireless communications

Thisarticlepresentsthedesign and fabrication ofa high power amplifierbased onwilkinson power combiner. A 45W basic amplifier module isdesigned usinglaterally-diffused metal-oxide semiconductor (LDMOS) fieldeffect transistor (FET) PTFA260451E transistor. Wilkinson power combineris used to combine two input powers toproduce 90W of power. Theproposed power amplifier is researched, designed and optimized usingadvanced design system(ADS) software.Experimental results show that thegain is 11.5 dB greater than at 2.45-3.0GHz frequency band and achieving maximum power gain of 13.5dB at 2.65GHz centre frequency; output power increased to 49.3dBm; Power added efficiency of 62.1% and good impedances matching: input reflection coefficient (S11)&amp;lt;-10dB, output reflection coefficient (S22)&amp;lt;-15dB. The designed amplifier can be used for4G, 5G mobile communications andS-band satellite communication.

Inductive Feedback Technique for Design of High Gain 0.18μm CMOS LNA for 5G Applications

A 26[Formula: see text]GHz low-noise amplifier (LNA) designed for 5G applications using 0.18[Formula: see text][Formula: see text]m CMOS technology is proposed in this paper. The circuit includes a common-source in the first stage to suppress the noise in the amplifier. The successive stage has a Cascode topology along with an inductive feedback to improve the power gain. The input matching network is designed to achieve the input reflection coefficient less than [Formula: see text]7dB at the intended frequency. The matching network at the output is designed using inductor–capacitor (LC) components connected in parallel to attain the output reflection coefficient of [Formula: see text]10[Formula: see text]dB. Due to the inductor added in feedback at the second stage. The [Formula: see text] obtained is 18.208[Formula: see text]dB at 26[Formula: see text]GHz with a noise figure (NF) of 2.8[Formula: see text]dB. The power supply given to the LNA is 1.8[Formula: see text]V. The simulation and layout of the presented circuit are performed using Cadence Virtuoso software.

A Common-Gate Current-Reuse UWB LNA for Wireless Applications in 90 nm CMOS

In this paper, a CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented. The proposed CMOS LNA is designed using common-gate (CG) topology at the first stage to achieve ultra wideband input matching. The common-gate has been cascaded with common-source (CS) current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power consumption. In order to ensure maximum power flow from CG input stage to gm boosted CS current-reused stage, parallel-series LC matching has been used. The output-matching network is used to improve the output reflection coefficient. The LNA is designed using standard 90 nm CMOS process for 3.1–10.6 GHz UWB. It exhibits a power-gain (S21) of 19.2–20.8 dB, an NF of 2.3–3.7 dB, a reverse-isolation (S12) of less − 53.8 dB and an S22 of less than − 6 dB for the entire UWB frequency range. The proposed LNA has an input reflection coefficient (S11) of less than − 10.6 dB for 3.1–10.6 GHz. It achieves input 1-dB compression point (P1dB) of − 17 dBm at 6 GHz and input third-order intercept point (IIP3) of − 8 dBm, while it consumes only 5.05 mW of power from a Vdd supply of 0.7 V.

High gain 0.18 μm-GaAs MMIC cascode-distributed low-noise amplifier for UWB application

This paper describes a design of 3 GHz–12 GHz MMIC distributed Low Noise Amplifiers (LNAs) for Ultra Wideband communications systems. The proposed circuit is a common source and cascode topology using a standard 0.18 μm ED02AH process from OMMIC foundry. The ultra-wideband LNA achieves a power gain of 16.9 ± 1.7 dB and an average noise figure of 2.9 ± 0.58 dB. The input and output reflection coefficients are less than −10 dB, the reverse gain S12 is less than −37dB and a high linearity IIP3 of [4–6.2] dBm. The chip area including testing pads is only about 1.3 × 1.3 mm2.

2.3–21 GHz broadband and high linearity distributed low noise amplifier

This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S21), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation and equalization of phase velocity techniques, to absorb their parasitic capacitances into the gate and drain transmission lines in order to achieve wide bandwidth and to enhance gain and linearity. The proposed broadband DA achieved an excellent gain in the flatness of 13.5 ± 0.2 dB, a low noise figure of 3.44 ± 1.12 dB, and a small group delay variation of ±19.721 ps over the range of 2.3–21 GHz. The input and output reflection coefficients S11 and S22 are less than −10 dB. The input compression point (P1dB) and input third-order intercept point (IIP3) are −1.5 dBm and 11.5 dBm, respectively at 13 GHz. The dissipated power is 282 mW and the core layout size is 2.2 × 0.8 mm2.

Design and Optimization of LNA Amplifier Based on HEMT GaN for X-Band Wireless-Communication and IoT Applications

Recently, the technology has evolved towards artificial intelligence world which include IoT (Internet of Things) and IoE (Internet of Everything) as communication between machines or between devices is possible. The development of these systems today requires electronic components capable of generating higher power and frequency levels, which is why new technologies have emerged to meet these needs, GaN HEMT technology. It has attracted a lot of attention for microwave power and high temperature applications. More recently, this technology has become a great interest to the international scientific community for the realization of low noise amplifiers which are the main components of wireless communication systems. In this paper, we modeled an LNA amplifier based on HEMT GaN transistors. This amplifier is unconditionally stable in the X-band (8–12) GHz with a gain of 38 dB, a noise factor does not exceed 2.4 dB and lower input and output reflection coefficients (S11, S22). at -14 dB and − 8 dB respectively. The designed amplifier can be integrated into radar systems, space communications systems and civilian-military radiolocation systems.

Analysis and design of low‐power and high‐gain complementary metal oxide semi‐conductor low noise amplifier operating at 28 GHz frequency for millimeter wave LEOS, local multiport distribution system and radar application

AbstractLow‐noise amplifier supports broadband standards with the advantage of low‐power, high‐gain, and low noise figure (NF). The low‐frequency design of this low‐noise amplifier (LNA) is used for multistandard wireless applications and the high‐frequency design of this LNA can be used in millimeter wave radar applications. This LNA is designed at the front‐end for amplification in the receiver side, so that signal to noise is adjusted on the multistandard receivers. LNA permits performance of the design with various parameters like NF, power efficiency, gain of the LNA, figure of merits, and linearity of the low‐noise amplifier. In 28 GHz, millimeter wave (mmW) circuits' design and analysis with high gain, low power, low NF, and wide bandwidth are preferred for radio frequency front end. This paper discusses, the Cascode design of CMOS LNA circuit at 28 GHz, and the novelty of the design is that it can operate at two different set of frequency bands (21 and 28 GHz) and it is multiband and multitunable. The design's conversion gain (S21) of 17.4 dB, NF of 4 dB, stability of 1, power optimized to 22.3 mW, and area of 0.399mm2 are reported. The input and output reflection coefficients are S11 ≤ −10 dB and S22 ≤ −10 dB. Electromagnetic simulation is performed using advanced design system tool. Output power of the proposed design is 2 dBm, transition frequency (fT) is 64GHz, and maximum operating frequency (fmax) is 96GHz. The observed results show that the proposed CMOS LNA design finds its suitability in mmW cloud radar application of mono‐pulse radar system and radar front‐end receiver circuits.

A 5.7 mW, UWB LNA for Wireless Applications Using Noise Canceling Technique in 90 nm CMOS

AbstractA 3–12 GHz ultra-wideband (UWB) low noise amplifier (LNA) is proposed in this paper. The first stage common-gate (CG), common-source (CS) noise canceling approach is used to achieve low noise-figure (NF). CG configuration at the input stage provides wideband input-matching. The noise of CG transistor is cancelled by systematically added two parallel CS transistors, whose outputs are cascoded in second stage. In order to achieve flat power gain (S21) response, a series peaking inductor is used in the second stage. The proposed LNA is designed in 90 nm CMOS process with chip-layout area of 0.467 mm2 and in comparison to the existing LNAs, it consumes a low power of 5.7 mW from a 1 V supply. The achieved input-reflection coefficient (S11) is &lt;−7.5 dB, output-reflection coefficient (S22) is &lt;−7.6 dB with NF &lt; 5.8 dB for 3–12 GHz UWB and third-order intercept point (IIP3) of −19 dBm. It achieves high and flat S21 of 20.84 ± 0.28 dB over 4.2–10 GHz, with NF ranging from 2.6–3.6 dB.

An AlGaN/GaN HEMT by a reversed pyramidal channel layer: Investigation and fundamental physics

AbstractIn this paper, an AlGaN/GaN HEMT with a reversed pyramidal channel layer (RPC‐HEMT) is proposed. The main purpose of the paper is an increase in the breakdown voltage of a conventional HEMT (C‐HEMT) to be suitable in high‐power applications. In the RPC‐HEMT, a reverse pyramidal channel layer in the high electric field traps the energetic carriers that cause the transistors to break. The steps decrease the carrier concentration across the two‐dimensional electron gas (2DEG) channel layer, especially under the gate contact. Therefore, the critical electrical field reduces by the uniform division of carrier mass and improves the breakdown voltage of the RPC‐HEMT by 32%. Besides, the maximum output power density of the new transistor improves compared with the conventional one. In addition, the radio frequency (RF) characteristics such as the cutoff frequency and maximum oscillation frequency of the RPC‐HEMT improve by the decline in the gate‐source capacitance. This article provides kink effects with the output reflection coefficient (S22) and the short‐circuit current gain (h21) to show how this anomalous phenomenon affects high‐frequency performance of devices. Finally, the proposed method makes the RPC‐HEMT appropriate for high‐power and high‐frequency applications.

Microwave Frequency Tripler using InGaAs HEMT Transistor

In this work, a 3x frequency multiplier in microstrip technology is presented. The frequency multiplier is used to generate 17.4GHz signal by multiplying 5.8GHz input and by using Indium gallium arsenide (InGaAs) High Electron Mobility Transistor (MGF4918D). The input and output reflection coefficients (S11 and S22) are less than -30 dB. The Rollet factor is greater than unity at the fundamental frequency 5.8GHz and in the 3rd harmonic which places at the frequency of 17.4GHz. The maximum conversion of the fundamental signal to the 3rd harmonic is given by an input power of 3.6dBm, gate-source voltage of -0.6V and drain-source voltage of 3V. The dissipated power Pdc is 45 mW and the surface of the chip occupied on a FR- 4 substrate is 7.3 x 3 cm2.