Output P1dB Research Articles

A millimeter‐wave broadband power amplifier with a tree‐like transistor structure using 0.15‐μm GaAs technology

AbstractIn this paper, a millimeter‐wave broadband high‐efficiency power amplifier (PA) for Ka‐band (26–32 GHz) using 0.15‐μm GaAs pseudomorphic high‐electron‐mobility transistor process is proposed. The PA utilizes a three‐stage cascade structure and adopts an RC series feedback network, which expands the bandwidth and ensures the circuit stability. To improve the output power and efficiency of the circuit, a tree‐like transistor structure is proposed. The power amplifier, it can provide 23.6 dBm output P1dB with 33.1% power‐added efficiency at 28 GHz with high linearity. The maximum small signal gain can reach 27 dB with 3‐dB bandwidth from 24 to 33 GHz for the measured results.

A Fully Integrated High Efficiency 2.4 GHz CMOS Power Amplifier with Mode Switching Scheme for WLAN Applications

A 3.3 V mode-switching RF CMOS power amplifier (PA) for WLAN applications is presented, which is integrated into a 55-nm bulk CMOS process. The proposed PA offers both static control and dynamic power control, allowing it to operate efficiently in both low-power and high-power modes. The pure low-power mode is achieved by reducing power cells, which are also used for linearization in high power mode. The low-power mode is achieved by reducing the number of power cells which are also used for linearization in the high-power mode. In the dynamic power control mode, the total AM–AM and AM–PM distortion is effectively compensated for by dynamically controlling the number of power cells and adjusting the matching input. The proposed PA achieves an output P1dB of 27.6 dBm with a PAE of 32.7% and an output P1dB of 17.7 dBm with a PAE of 10% in high-power and low-power modes, respectively. It is measured with an 802.11 n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 19 dBm under an error-vector-magnitude (EVM) of −27 dB.

Destructive Testing for Reliability Analysis at High-Power Microwave in GaAs/InGaP Hetero-Junction Bipolar Transistor

The destructive testing for reliability analysis at high-power microwave (HPM) in the GaAs/InGaP hetero-junction bipolar transistor (HBT) has been rarely investigated although it has a significant impact on their performance and reliability against HPM. This paper employs the experimental measurements to study the HPM damage process. We first establish the experiment platform for injecting the HPM to the GaAs/InGaP HBT which has the P1dB output power of +15.5 dBm to acquire the damage threshold. It is found that with the increasing of the input power, the output waveforms are gradually distorted. In particular, when the input power increases to 45 dBm, the S parameters of the GaAs/InGaP HBT chip show that it is totally destroyed. The experiment results show that the damage threshold of the HBT decreases with the increase of the pulse width, and the decrease rate of the damage threshold gradually slowed down with the increases of pulse width. The damage threshold can be reduced by increasing the pulse number from 1 to 10.

A lumped‐element balun design with multi‐interference suppression for push–pull power amplifier

SummaryIn this article, a lumped‐element balun with multi‐interference suppression is implemented and presented. Originated from the conventional lattice LC balun, the balun combining two Π‐networks is expended to four new topologies. By constructing frequency traps and out‐of‐phase combining pathways, the new topologies can realize two‐ or three‐interference suppression while maintaining well‐matched input/output impedances. The concept is studied theoretically in both even and odd mode circuits, and analytical design equations are also derived. Based on the design theory, four interference suppression balun topologies are proposed for push–pull power amplifiers. To verify the design concept, two of the four topologies working at 1 GHz are prototyped and measured. The measured results agree well with the analysis and simulation results. The two baluns both achieve good performance with low insertion loss better than −3.9 dB, low return loss less than −13.6 dB, good interference suppression more than 24.7 dB, and small phase unbalance less than 0.8°. Furthermore, the proposed balun is used in a gallium nitride push–pull power amplifier to validate the 2nd and 3rd harmonic suppression. The amplifier works at 1 GHz with a typical gain of 16.7 dB. At least −45 dBc interference suppression, 52.6% power‐added efficiency, and 34.6 dBm P1dB output power are obtained.

C-Band GaN Dual-Feedback Low-Noise Amplifier MMIC with High-Input Power Robustness

In this paper, using the 0.2 μm ETRI GaN HEMT process, we developed a C-band GaN dual-feedback low-noise amplifier MMIC for an RF receiver module that requires high-input power robustness. By applying a feedback microstrip line at the source of the transistor and series resistor-capacitor (RC) feedback between the gate and the drain of the transistor, we obtained stable amplifier operation and a compromised impedance trace for both input impedance matching and noise matching while suppressing performance degradation of the maximum available gain and minimum noise figure. The developed low-noise amplifier MMIC, which implements simple matching circuits by using biasing elements as matching elements, had a linear gain of more than 21.4 dB and a noise figure of less than 1.91 dB in the wide bandwidth of 4.3–7.4 GHz. Under the single-tone power test, the low-noise amplifier MMIC had an output P1dB of 14.3–20.1 dBm, and the two-tone intermodulation distortion measurement exhibited an input third-order intercept point (IIP3) of 2.2–5.6 dBm in the same frequency range as the above.

Power Limiter with PIN Diode Embedded in Cavity to Minimize Parasitic Inductance

This letter introduces a power limiter that limits the input power to protect the receiver when a large power enters the radio frequency receiver. When the power limiter receives a large power signal, a positive-intrinsic-negative (PIN) diode is turned on to limit the input power by lowering the impedance. We analyzed the characteristics of the power limiter according to the method of connecting the PIN diode in parallel with the input and output transmission lines of the power limiter. By embedding a PIN diode into the cavity and minimizing the length of the wire, a power limiter was designed and implemented to minimize parasitic inductance. In the S-band, the proposed power limiter’s insertion loss was below 0.5 dB, and the reflection loss characteristics were below 15 dB. Furthermore, it achieved an output P1dB of 21.8 dBm at 3.5 GHz.

A CMOS 4‐Element Ku‐Band Phased‐Array Transceiver

This paper presents a Ku-Band fully differential 4-element phased-array transceiver using a standard 180-nm CMOS process. Each transceiver is integrated with a 5-bit phase shifter and 4-bit attenuator for high-resolution radiation manipulation. The front-end system adopts time-division mode, and hence two low-loss T/R switches are included in each channel. At room temperature, the measured root-mean-square (RMS) phase error is less than 5.5°. Furthermore, the temperature influence on passive switched phase shifters is analyzed. Meanwhile, an extra phase-shifting cell is developed to calibrate phase error varying with the operating temperatures. With the calibration, the RMS phase error is reduced by 7° at −45 ℃, and 5.4° at 85 ℃. The RMS amplitude error is less than 0.92 dB at 15−18 GHz. In the RX mode, the tested gain is 9.6±1.1 dB at 16.5 GHz with a noise figure of 10.9 dB, and the input P1dB is −15 dBm, while the single-channel's gain and output P1dB in the TX mode are 11.3±0.4 dB and 9.4 dBm at 16.1 GHz, respectively. The whole chip occupies an area of 5×4.2 mm2 and the measured isolation between each two adjacent channels is lower than −23.1 dB.

A 6–12 GHz wideband low‐noise amplifier GaAs FET design with 0.8‐dB average NF and 25‐dB gain

AbstractLow‐noise amplifiers (LNAs) with low‐noise performance are critical components in communication systems. However, reaching a high level of performance is difficult. This study introduces a LNA for radio frequency front‐end receivers with a frequency range of 6–12 GHz. The planned LNA contains a two‐stage high‐electron‐mobility transistor cascade amplifier with a minimum measured noise figure of 0.8 dB and a peak gain of 25 dB at room temperature. The proposed LNA is based on a gallium arsenide field‐effect transistor transistor (CE3512K2) because of its good low‐noise performance at microwave frequency bands. The measured results demonstrate that the proposed LNA is perfectly matched over the whole operational frequency spectrum of the input/output ports (|S11|<−10 dB, |S22|<−10 dB). Also, output P1dB and input P1dB are, respectively, +4 and −19 dBm for this design. The suggested LNA is suitable for C and X frequency band applications.

A Compact 60GHz Power Amplifier in 65nm CMOS Technology

A compact 60GHz power amplifier chip in 65nm CMOS technology of three-stage common source structure is presented. The first two amplifiers offer sufficient gain to pre-amplify the small input power. The third stage amplifier uses two sets of differential pairs to achieve power synthesis. On-chip transformer coupling is adopted to realize inter-stage impedance matching as well as input and output matching. The compact structure of on-chip transformer can reduce the chip size and improve the integration degree. The measured small signal gain at 60GHz of 22.3dB, the saturation power of 20.2dBm, the output P-1dB of 17.3dBm, the PAE of 14%, and the core area is 0.19mm2. The power amplifier can be used in high-speed short-range wireless communication system to enhance communication data transmission capacity.

유도성 소스 축퇴를 이용한 X-대역 GaN MMIC 저잡음 증폭기

In this study, an X-band GaN monolithic microwave integrated circuit (MMIC) low-noise amplifier is designed and fabricated for RF transceiver modules using a 0.2 μm ETRI GaN HEMT process. Through the application of a feedback microstrip line at the source of the transistor, the amplifier operation is stabilized, and a compromised impedance trace of the input impedance and noise matching is obtained, which minimizes the degradation of the maximum available gain and minimum noise figure. The developed MMIC low noise amplifier, which uses simple matching and biasing circuits as matching elements, exhibits a linear gain of more than 20 dB and a noise figure of 1.5～2.0 dB from 8.7 to 11.5 GHz. A single-tone power test shows an output P1dB of 17.1～24.3 dBm, and a two-tone IMD measurement shows an output IP3 of 27.4～32.4 dBm in the same frequency range.

A Closed-Loop Reconfigurable Analog Baseband Circuitry With Open-Loop Tunable Notch Filters to Improve Receiver Tx Leakage and Close-in Blocker Tolerance

This paper presents an analog baseband (ABB) circuit in a 0.13 μm SiGe technology for transmitter leakage cancellation and close-in blocker suppressions in fully duplex (FD) frequency-modulated continuous-wave (FMCW) radar. This ABB comprises a programmable gain amplifier (PGA) and a cascaded LPF/Notch hybrid, which incorporates a closed-loop (CL) reconfigurable low-pass filter (LPF) and an open-loop (OL) tunable notch filter. The adopted key topologies include active-RC bi-quads and Gm-C ones. In an FD FMCW transceiver, Tx leakage and close-in blockers are difficult to be eliminated in the RF domain, especially when leakage/blockers are very close to desired signals or even in-band in the frequency domain. This LPF/notch hybrid is proposed to solve this issue. The LPF and PGA provide bandwidth (BW)/gain programmability, while the Gm-C bi-quad provides adaptable center frequency for a notch filter. With this adaption, the notch filter could be adjusted to match the leakage/blocker offset frequency. Thus, digitally discrete programmability and analog continuous tuning capability are combined in this solution for improving the overall front-end interference robustness without de-sensitizing the Rx. Furthermore, the order of LPF/notch hybrid is programmable from 2 to 10 with a step of 2 for different rejection levels of interferences. The measured chip achieves a -3dB bandwidth of 6 21 MHz with 4-bit digital control and 1 MHz/step programmability, and a voltage gain of 0 70 dB with 9-bit digital control (3-bit from pre-amplifier, and 6-bit from PGA with 1 dB/step). With the condition of 15 dB gain, output P-1dB is 11.8 dBm@3MHz, and the output IP3 is 20.8 dBm@3MHz.

A 28 GHz GaAs front‐end IC with single positive supply voltage

AbstractThis paper presents 28 GHz GaAs front‐end IC for 5G beamforming systems with single positive supply voltage. A 28 GHz front‐end IC consists of a 3‐stage power amplifier, a 3‐stage low noise amplifier and two reflective type single pole double throw switches in 0.15 μm enhancement‐mode (E‐mode) GaAs pHEMT technology. The proposed 28 GHz front‐end IC is controlled only with single positive supply voltage. The measured front‐end IC Tx mode gain and Rx mode gain are 16.3 dB and 16.8 dB at 28 GHz, respectively. The achieved output P1dB and saturation power (PSAT) in Tx mode are 18 dBm and 21 dBm, respectively. The achieved input P1dB and noise figure in Rx mode are −8 dBm and 3 dB, respectively. The 28 GHz GaAs front‐end IC consumes DC current of 216 mA in Tx mode at 4 V supply voltage and 20 mA in Rx mode at 2.5 V supply voltage. The proposed 28 GHz front‐end IC chip size is 2.5 x 2.2 mm2.

A new design strategy for bandwidth and efficiency enhancement in KA band CMOS power amplifier

PurposeThe purpose of this paper is to propose a new design strategy to enhance the bandwidth and efficiency of the power amplifier.Design/methodology/approachTo realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka-band, i.e. the frequency range of 26.5-40 GHz. To design the power amplifier, first, a power divider (PD) with a very wide bandwidth, i.e. 1-40 GHz, was designed to cover the whole Ka-band. The designed Doherty power amplifier consisted of two different amplification paths called main and auxiliary. To amplify the signal in each of the two pathways, a cascade distributed power amplifier was used. The main reason for combining the distributed structure and cascade structure was to increase the gain and linearity of the power amplifier.FindingsMeasurements results for designed power dividers are in good agreement with simulations results. The simulation results for the introduced structure of the power amplifier indicated that the gain of the proposed power amplifier at the frequency of 26-35 GHz was more than 30 dB. The diagram of return loss at the input and output of the power amplifier in the whole Ka-band was less than −8dB. The maximum power-added efficiency (PAE) of the designed power amplifier was 80%. The output P1dB of the introduced structure was 36 dB and the output power of the power amplifier was 36 dBm. Finally, the IP3 value of the power amplifier was about 17 dB.Originality/valueThe strategy presented in this paper is based on the usage of Doherty and distributed structures and a new wideband power divider to benefit from their advantages simultaneously.

A Ku-Band GaAs Multifunction Transmitter and Receiver Chipset

This paper presents a Ku-band monolithic multifunction transmitter and receiver chipset fabricated in 0.25-μm GaAs pseudomorphic high-electron mobility transistor technology. The chipset achieves a high level of integration, including a 4-bit 360° digital phase shifter, 5-bit 15.5-dB digital attenuator, amplifier and 9-bit digital serial-to-parallel converter for digital circuit control. Since the multifunction chipset includes a medium power amplifier and a low-noise amplifier, it features high P1dB and low noise figures over the full Ku-band frequencies. The multifunction transmitter shows a peak gain of 16.5 dB with output P1dB of 19.2 dBm at 15 GHz. The multifunction receiver shows a peak gain of 17.3 dB with noise figure of 2.5 dB at 15 GHz. The attenuation range is 15.5 dB with a step of 0.5 dB and the phase shift range is 360° with a step of 22.5°. Each chip area of the transmitter and receiver is 4.2 × 2.8 mm2.

Compact 4‐bit GaAs Ku‐band core chips for phased arrays

AbstractIn this letter, we present an Rx core chip and a Tx core chip for Ku‐band phased arrays, which are designed and fabricated using the commercial 0.25‐μm GaAs pHEMT foundry service. Each of the Rx core chip and the Tx core chip has a 4‐bit phase shifter driven by an on‐chip serial‐to‐parallel (SPC) converter. The on‐chip SPC provides the serial interface with an external controller. The Rx core chip shows a gain >10 dB, a noise figure less than 2 dB at a frequency range of 10.7 to 12.75 GHz and for all phase states of the 4‐bit Rx phase shifter. The Tx core chip shows a gain >10 dB, an output P1dB of about 13 dBm at a frequency range of 13.5 to 15.5 GHz and for all phase states of the 4‐bit Tx phase shifter. The Rx core chip and the Tx core chip have the same size of 1.75 × 1.75 mm2, which we believe the state of the art size among the presented GaAs core chips.

A 5.8‐17.6 GHz cascaded bi‐directional distributed gain amplifier utilizing asymmetric stages in 65 nm CMOS

AbstractA cascaded bidirectional distributed gain amplifier (BDGA) with asymmetrical stages has been reported. By cascading two unit BDGAs using a common source (CS) stage in the middle, the BDGA benefits the multiplicative gain enhancement while it can still achieve a wide bandwidth owing to the distributed nature of the two BDGAs. Each gain stage of the BDGA is composed of the CS output stage to enhance the linearity in parallel with the cascode input stage to improve noise performance by providing higher gain. The proposed circuit architecture is fabricated in a 65 nm CMOS. The measurements exhibit a gain of 10.5 dB, and the 3‐dB bandwidth from 5.8 to 17.6 GHz. The measured output P1dB is 6.8 dBm along with 9.3 dBm of the saturated output power at 10 GHz. The circuit draws 75 mA from a 1.2 V supply and occupies 1.1 × 0.6 mm2 of the chip area.

A broadband GaAs pHEMT low noise driving amplifier with current reuse and self-biasing technique

A K/Ka-band two-stage low noise driving amplifier using a 0.15 μm GaAs pHEMT for low noise technology is designed and fabricated. In order to achieve broadband driving capability with low power consumption, current reuse technique is adopted to feed both transistors with the same DC power supply, which theoretically cuts the total current consumption in half. In addition, self-biasing technique is utilized to minimize both external power supply pads and chip footprint, which reduces the number of supply pads to a minimum of two (1 power pad and 1 ground pad). The circuit topology analysis and design procedures are also presented with an emphasis on noise figure and P1dB optimization. The low noise driving amplifier demonstrates a − 3 dB bandwidth of wider than 11 GHz, a power gain of 17 dB, an in-band mean noise figure of 2.2 dB and an in-band mean output P1dB of 6 dBm. The DC power consumption is 9.1 mA@3.3 V power supply. The chip size is 1 mm × 1.5 mm with only 1 external DC feed pad (3.3 V) and 1 ground pad (0 V). With the performance comparable to typical two-stage dual-bias low noise driving amplifier counterparts, the proposed MMIC is more attractive to chip/system users in volume-limited and power-contrained applications.

A 5G 28-GHz Common-Leg T/R Front-End in 45-nm CMOS SOI With 3.7-dB NF and −30-dBc EVM With 64-QAM/500-MBaud Modulation

This paper presents a 28-GHz common-leg phased-array front-end in 45-nm CMOS silicon on insulator with transmit and receive capabilities. The design alternates cascode amplifiers with passive switched- $LC$ phase-shifter cells to result in 5-bit phase control with an rms phase and gain error <4° and <0.8 dB, respectively, at 24–30 GHz, over 32 phase states. The front-end has 2- and 3-bit variable gain amplifiers with 7.5-dB total gain control, without affecting the system noise figure (NF). Two low-loss high-linearity single-pole double-throw switches are used to switch between transmit and receive modes. In the receive (Rx) mode, the measured gain, NF, input 1-dB compression point (P1dB), and input third-order intercept point are 16 dB, 3.7 dB, −15 dBm, and −7 dBm, respectively, with 54-mW dc power consumption. In the transmit (Tx) mode, measurements show 16.5-dB gain, an output P1dB of 8 dBm, and an output IP3 of 16 dBm with 100-mW dc power consumption. The error-vector magnitude and adjacent-channel-power-ratio measurements demonstrate quadrature phase-shift keying, 16-quadrature amplitude modulation (QAM), 64-QAM, and 16-QAM orthogonal frequency-division multiplexing modulations with several symbol-rates reaching up to 8 Gb/s data-rate for both the Rx and Tx modes at 2- and 5-dB back-off. The application areas are in fifth-generation phased arrays requiring high-linearity receivers and using external front-end modules for added transmit power.

A Highly Linear Dual-Gain CMOS Low-Noise Amplifier for &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$X$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Band

A highly linear X-band low-noise amplifier (LNA) is proposed and implemented in a standard 0.18- $\mu \text{m}$ CMOS technology. The LNA features both high- and low-gain operation modes. In its normal high-gain mode, the LNA shows a small-signal gain of 13.6 dB with an IIP3 of +9.5 dBm and a noise figure of 4.7 dB. The two-stage amplifier draws 90 mA from the 3.3-V power supply to achieve +14.8 dBm output P1dB (+2.2 dBm input P1dB). In the low-gain mode, the gain is reduced by about 10 dB to further enhance the linearity and to accommodate very large blockers. Accordingly, the input P1dB is enhanced to +13.7 dBm while the noise figure is increased by 8.1 dB. A technique is also introduced to maintain the input matching when the LNA is switched to operate in the low-gain mode.

24 GHz 1Tx 2Rx FMCW 송수신기 설계

This paper presents a 24-GHz frequency-modulated continuous wave(FMCW) radar transceiver with two Rx and one Tx channels in 65-nm complementary metal-oxide-semiconductor(CMOS) process and implemented it on a radar system using the developed transceiver chip. The transceiver chip includes a 14× frequency multiplier, low-noise amplifier, down-conversion mixer, and power amplifier(PA). The transmitter achieves &gt;10 dBm output power from 23.8 to 24.36 GHz and the phase noise is −97.3 GHz/Hz at a 1-MHz offset. The receiver achieves 25.2 dB conversion gain and output P1dB of −31.7 dBm. The transceiver consumes 295 mW of power and occupies an area of 1.63×1.6 mm2. The radar system is fabricated on a low-loss Duroid printed circuit board(PCB) stacked on the low-cost FR4 PCBs. The chip and antenna are placed on the Duroid PCB with interconnects and bias, gain blocks and FMCW signal-generating circuitry are mounted on the FR4 PCB. The transmit antenna is a 4×4 patch array with 14.76 dBi gain and receiving antennas are two 4×2 patch antennas with a gain of 11.77 dBi. The operation of the radar is evaluated and confirmed by detecting the range and azimuthal angle of the corner reflectors.