Fast Fourier Transform Output Research Articles

A Computationally Efficient Direct Position Determination Algorithm Based on OFDM System

Based on the orthogonal frequency division multiplexing (OFDM) system, a computationally attractive implementation for the traditional single source maximum likelihood (SML) direct position determination (DPD) algorithm is proposed. The proposed algorithm implements fast Fourier transform (FFT) to the received frequency-domain signals after deconvolution. Then, the cost function for all points can be obtained from the same FFT output set. As a consequence, some repeated calculation in the traditional SML DPD algorithm is avoided. Simulation results demonstrate that the proposed modified SML DPD algorithm can achieve a comparable performance to traditional SML-DPD while significantly reducing the computational complexity.

Frequency domain analysis of MFCC feature extraction in children’s speech recognition system

Abstract —The research on speech recognition systems currently focuses on the analysis of robust speech recognition systems. When the speech signals are combined with noise, the recognition system becomes distracted, struggling to identify the speech sounds. Therefore, the development of a robust speech recognition system continues to be carried out. The principle of a robust speech recognition system is to eliminate noise from the speech signals and restore the original information signals. In this paper, researchers conducted a frequency domain analysis on one stage of the Mel Frequency Cepstral Coefficients (MFCC) process, the Fast Fourier Transform (FFT), in children's speech recognition system. The FTT analysis in the feature extraction process determined the effect of frequency value characteristics utilized in the FFT output on the noise disruption. The analysis method was designed into three scenarios based on the value of the employed FFT points. The differences between scenarios were based on the number of shared FFT points. All FFT points were divided into four, three, and two parts in the first, second, and third scenarios, respectively. This study utilized children's speech data from the isolated TIDIGIT English digit corpus. As comparative data, the noise was added manually to simulate real-world conditions. The results showed that using a particular frequency portion following the scenario designed on MFCC affected the recognition system performance, which was relatively significant on the noisy speech data. The designed method in the scenario 3 (C1) version generated the highest accuracy, exceeded the accuracy of the conventional MFCC method. The average accuracy in the scenario 3 (C1) method increased by 1% more than all the tested noise types. Using various noise intensity values (SNR), the testing process indicates that scenario 3 (C1) generates a higher accuracy than conventional MFCC in all tested SNR values. It proves that the selection of specific frequency utilized in MFCC feature extraction significantly affects the recognition accuracy in a noisy speech.

Study of the truncation strategy in the FPGA of a solar radio digital receiver

Abstract Computation resource is the limiting factor in higher operational accuracy of field-programmable gate arrays (FPGAs) in solar radio digital receivers. The data truncation strategy which determines the accuracy of data is then the essential technology in the design of a receiving system. Based on the solar radio spectrometer (dual channel, 14 bit, 1.25 gigasamples per second) at the Chashan Solar Radio Observatory (CSO), this paper presents a data truncation strategy which can realize real-time solar radio observation (35–40 GHz) with high time and frequency resolution as well as a large dynamic range, and at the same time saves the computation resource to a large extent. Simulations of truncations during signal processing are carried out in MATLAB, and the best truncation mechanisms are deduced for windowing and fast Fourier transform (FFT). Using the simulation results, the best truncation strategies have been implemented in the solar radio receiver at CSO with the result that the best truncation bits for the windowing operation are [27 : 14], with an error of 2.5 × 10−4, and the best truncation bits for the FFT output are [20 : 5] with an error of 1.5 × 10−3. Compared with the processing of full-precision data, occupation of the computation resources in the FPGA can be reduced significantly. For instance, the lookup table, lookup table RAM, flip flop, and digital signal processing slices are reduced by 7.36%, 14.65%, 8.38%, and 24.94%, respectively, which guarantees broad-band real-time solar radio observations (35–40 GHz).

Scheduling of Data Access for the Radix-2k FFT Processor Using Single-Port Memory

The scheduling of data access plays a prominent part in a memory-based fast Fourier transform (FFT) processor. In this article, a conflict-free data-access scheme is proposed and applied to implement a radix-2k FFT processor with the computing parallelism being the power of 2. The proposed FFT module exploits single-port RAMs to retain the area efficiency, and it has the following hardware-friendly features. First, the memories are merged into four banks under the arbitrary computing parallelism, which helps to circumvent the complicated data-routing circuit. Second, the parallelism of the input/output (I/O) data can be enlarged to the internal computing parallelism, which accelerates the data update and enhances the throughput capability. Furthermore, the concurrent I/O operation that overlaps the storage of the FFT input with the supply of FFT output in the same memory sets is allowed, which minimizes the memory occupation for the management of continuous data flow. Based on the testing on the field-programmable gate array (FPGA) and ASIC implementation using the SMIC 40-nm CMOS technology, it is demonstrated that the proposed FFT processor can offer high throughput and simultaneously achieve remarkable area and power efficiency.

FPGA Implementation of Radix-2 based FFT Architecture for Real-Valued signal processing

This paper investigates the various pipelined FFT architectures based on radix-2, radix-22 & radix-23 algorithms. The implemented FFTs are designed by employing techniques such as folded transform and register minimization. It maximizes the utilization of hardware resource and reduces the number of adders. It requires less area and achieves high throughput and low latency. For higher values of N, the FFT (Fast Fourier Transform) architecture has many butterfly structures which has been optimized. The FFT outputs are usually obtained in a bit reversed order and a new approach for reordering the bit-reversed orders has been proposed.

Fractal dimension to classify the heart sound recordings with KNN and fuzzy c-mean clustering methods

The heart abnormalities can be detected from heart sound. A heart sound can be heard directly with a stethoscope or indirectly by a phonocardiograph, a machine of the heart sound recording. This paper presents the implementation of fractal dimension theory to make a classification of phonocardiograms into a normal heart sound, a murmur, or an extrasystole. The main algorithm used to calculate the fractal dimension was Higuchi’s Algorithm. There were two steps to make a classification of phonocardiograms, feature extraction, and classification. For feature extraction, we used Discrete Wavelet Transform to decompose the signal of heart sound into several sub-bands depending on the selected level. After the decomposition process, the signal was processed using Fast Fourier Transform (FFT) to determine the spectral frequency. The fractal dimension of the FFT output was calculated using Higuchi Algorithm. The classification of fractal dimension of all phonocardiograms was done with KNN and Fuzzy c-mean clustering methods. Based on the research results, the best accuracy obtained was 86.17%, the feature extraction by DWT decomposition level 3 with the value of kmax 50, using 5-fold cross validation and the number of neighbors was 5 at K-NN algorithm. Meanwhile, for fuzzy c-mean clustering, the accuracy was 78.56%.

Fault Identification in Doubly fed Induction Generator using FFT and Neural Networks

This paper presents a fault identification system for doubly fed induction generator. The proposed system is designed to identify single-phase faults and load switching events on an isolated load. Firstly, the system preprocess the stator line current data by the fast Fourier transform (FFT). In order to reduce the dimensionality of the FFT output data, the principal component analysis method is used. The fault identification stage is based on artificial neural network (ANN). Also, a post-processing is employed in order to increase the network reliability, which reduces the error of ANN. The proposed system is simulated and experimentally validated on different voltage, speed and load conditions.

새로운 DIT Radix-4 FFT 구조 및 구현

FFT(Fast Fourier Transform) 알고리즘에는 DIT(Decimation-In-Time)와 DIF(Decimation-In-Frequency)가 있다. DIF 알고리즘은 Radix-2/4/8 등의 다양한 종류와 그 구현 방법이 개발되어 사용되고 잇으나, DIT 알고리즘은 순차적인 출력을 낼 수 있는 장점이 있음에도 불구하고 다양한 알고리즘이 연구되지 못하였다. 이 논문에서는 새로운 DIT Radix-4 FFT의 나비연산기(butterfly) 구조를 제안하고 검증하였다. 제안 구조를 사용하여 64-point FFT 구조를 설계하고 Verilog로 코딩하여 구현함으로써 제안 구조의 효용성을 입증하였다. 48개의 곱셈기를 사용하여 합성하였으며 678만 게이트 수를 나타내었다. 따라서 제안된 DIT Radix-4 FFT 구조는 순차적인 FFT 출력을 필요로 하는 OFDM 통신용 SoC(System on a Chip)에 사용될 수 있을 것이다. 【Two basic FFT(Fast Fourier Transform) algorithms are the DIT(Decimation-In-Time) and the DIF (Decimation-In-Frequency). In spite of the advantage of the DIT algorithm is to generate a sequential output, various structures have not been made. In this paper, a new DIT Radix-4 FFT butterfly structure are proposed and implemented using Verilog coding. Through synthesis, it is shown that the 64-point FFT is implemented by 6.78 million gates. Since the proposed FFT structure has the advantage of a sequential output, it can be used in OFDM communication SoC(System on a Chip) which need a high speed FFT output.】

FPGA-based voltage and current dual drive system for high frame rate electrical impedance tomography.

Electrical impedance tomography (EIT) is used to image the electrical property distribution of a tissue under test. An EIT system comprises complex hardware and software modules, which are typically designed for a specific application. Upgrading these modules is a time-consuming process, and requires rigorous testing to ensure proper functioning of new modules with the existing ones. To this end, we developed a modular and reconfigurable data acquisition (DAQ) system using National Instruments' (NI) hardware and software modules, which offer inherent compatibility over generations of hardware and software revisions. The system can be configured to use up to 32-channels. This EIT system can be used to interchangeably apply current or voltage signal, and measure the tissue response in a semi-parallel fashion. A novel signal averaging algorithm, and 512-point fast Fourier transform (FFT) computation block was implemented on the FPGA. FFT output bins were classified as signal or noise. Signal bins constitute a tissue's response to a pure or mixed tone signal. Signal bins' data can be used for traditional applications, as well as synchronous frequency-difference imaging. Noise bins were used to compute noise power on the FPGA. Noise power represents a metric of signal quality, and can be used to ensure proper tissue-electrode contact. Allocation of these computationally expensive tasks to the FPGA reduced the required bandwidth between PC, and the FPGA for high frame rate EIT. In 16-channel configuration, with a signal-averaging factor of 8, the DAQ frame rate at 100 kHz exceeded 110 frames s (-1), and signal-to-noise ratio exceeded 90 dB across the spectrum. Reciprocity error was found to be for frequencies up to 1 MHz. Static imaging experiments were performed on a high-conductivity inclusion placed in a saline filled tank; the inclusion was clearly localized in the reconstructions obtained for both absolute current and voltage mode data.

Fixed-Point Analysis and Parameter Selections of MSR-CORDIC With Applications to FFT Designs

Mixed-scaling-rotation (MSR) coordinate rotation digital computer (CORDIC) is an attractive approach to synthesizing complex rotators. This paper presents the fixed-point error analysis and parameter selections of MSR-CORDIC with applications to the fast Fourier transform (FFT). First, the fixed-point mean squared error of the MSR-CORDIC is analyzed by considering both the angle approximation error and signal round-off error incurred in the finite precision arithmetic. The signal to quantization noise ratio (SQNR) of the output of the FFT synthesized using MSR-CORDIC is thereafter estimated. Based on these analyses, two different parameter selection algorithms of MSR-CORDIC are proposed for general and dedicated MSR-CORDIC structures. The proposed algorithms minimize the number of adders and word-length when the SQNR of the FFT output is constrained. Design examples show that the FFT designed by the proposed method exhibits a lower hardware complexity than existing methods.

Iterative Decision-Directed Joint Frequency Offset and Channel Estimation for KSP-OFDM

We propose an iterative decision-directed joint frequency offset (FO) and channel estimation algorithm in a known symbol padding (KSP) orthogonal frequency division multiplexing (OFDM) system, where the guard interval is filled with pilot symbols. Besides those time domain pilot symbols, some additional pilot symbols are transmitted on the pilot carriers. The decision-directed algorithm is initialized by pilot-aided FO estimation without channel knowledge. We propose a possible initialization algorithm that operates in the frequency domain (FD). After the initialization phase, the iterative decision-directed estimation algorithm is applied. For the channel estimation step, an existing pilot-aided channel estimation algorithm is extended to a decision-directed algorithm which uses the Fast Fourier Transform outputs at both the pilot and data carrier positions. For the uncoded case, the proposed iterative decision-directed joint FO and channel estimation algorithm reaches the bit error rate performance of a receiver with perfect synchronization and perfect channel knowledge. For a coded system, there is small loss in performance of less than 1 dB when our proposed algorithm is applied compared to a receiver with perfect knowledge about the FO and the channel.

MAP Receiver with Spatial Filters for Suppressing Cochannel Interference in MIMO-OFDM Mobile Communications

This paper proposes joint maximum a posteriori (MAP) detection and spatial filtering for MIMO-OFDM mobile communications; it offers excellent receiver performance even over interference-limited channels. The proposed joint processor consists of a log likelihood generator and a MAP equalizer. The log likelihood generator suppresses cochannel interference by spatially filtering received signals and provides branch metrics of transmitted signal candidates. Using the branch metrics, the MAP equalizer generates log likelihood ratios of coded bits and performs channel decoding based on the MAP criterion. In the first stage, the log likelihood generator performs spatio-temporal filtering (STF) of the received signals prior to the fast Fourier transform (FFT) and is referred to as preFFT-type STF. Estimation of parameters including tap coefficients of the spatio-temporal filters and equivalent channel impulse responses of desired signals is based on the eigenvalue decomposition of an autocorrelation matrix of both the received and transmitted signals. For further improvement, in the second stage, the generator performs spatial filtering (SF) of the FFT output and is referred to as postFFT-type SF. Estimation of both tap coefficients of the spatial filters and channel impulse responses employs the recursive least squares (RLS) with smoothing. The reason for switching from preFFT-type STF into postFFT-type SF is that preFFT-type STF outperforms postFFT-type SF with a limited number of preamble symbols while postFFT-type SF outperforms preFFT-type STF when data symbols can be reliably detected and used for the parameter estimation. Note that there are two major differences between the proposed and conventional schemes: one is that the proposed scheme performs the two-stage processing of preFFT-type STF and postFFT-type SF, while the other is that the smoothing algorithm is applied to the parameter estimation of the proposed scheme. Computer simulations demonstrate that the proposed scheme can achieve excellent PER performance under interference-limited channel conditions and that it can outperform the conventional joint processing of preFFT-type STF and the MAP equalizer.

A novel generic fast Fourier transform pruning technique and complexity analysis

The fast Fourier transform (FFT) is an essential tool in digital signal processing and communications. In the applications of the FFT where the required outputs are very sparse, for example, in digital filtering, one may only require the spectrum corresponding to certain bins of the FFT or in narrow frequency windows. In these cases, most of the FFT outputs are not required. Some pruning algorithms have been proposed to deal with such cases. However, most of the pruning algorithms require that the outputs be in continuous windows. This paper develops a traced FFT Pruning method (TFFTP), which is a novel technique and does not require this condition. Under some circumstances, considerable savings in computational complexity and power consumption can be realized using the TFFTP compared to the FFT. This paper derives the average number of butterflies that need to be executed when only k/sub in/ input or/and k/sub out/ output bins of an N point FFT, where k/sub in//spl les/N, or/and k/sub out//spl les/N are required. This method is then extended to arbitrary radix FFT pruning and simultaneous input and output pruning case.

Radar processing gain improvement over frequency using the discrete wavelet transform

The range-gated fast Fourier transform (FFT) is the most common implementation of the optimum receiver for radar signals having random phase, frequency, and arrival time. In practice, the receiver is only optimum for input signals with frequency equal to an FFT bin frequency. Here the discrete wavelet transform (DWT) is applied to the FFT output to recover processing gain (PG) lost for nonoptimum input signals. Since the FFT and FFT-DWT have optimum performance for different input frequencies, these algorithms can be combined by binary integration (BI) to result in a dramatically improved worst case PG over frequency.

A Dynamic Electroencephalogram Frequency Analyzer

A microprocessor is used for real-time frequency analysis of an EEG amplifier output through the use of a 32-point fast Fourier transform (FFT). The sixteen frequency components are gain equalized, then summed into the conventional delta, theta, alpha, and beta bands. A simultaneous display of successive processed FFT outputs on a storage oscilloscope along with base line references is of substantial aid in determining the relative activity in each. Simple changes in test conditions show considerable activity in the delta, theta, and beta bands. The alpha band surprisingly was relatively constant for many subjects through a large range of test conditions. Permanent copy is provided by photographing the CRT display or by direct printout of intermediate and/or final results on a Teletype or high-speed printer. System design parameters and preliminary results are discussed.

Frequency Domain Interpolation

A formula is derived for interpolation between output samples of a fast Fourier transform (FFT), i.e., in the frequency domain. Such a formula is useful for obtaining greater frequency resolution when two coarse FFT outputs are available. Consideration is also given to the effect of such interpolation on a weighted FFT.