Output Buffered ATM Switch Research Articles

Fast scheduling algorithm for input and output buffered ATM switch with multiple switching planes

A new scheduling method is presented, two-dimensional round-robin scheduling with multiple selections (2DRRMS), for an input and output buffered ATM switch. In the switch, both input and output ports are divided into several groups and multiple switching planes are used. In the 2DRRMS method the multiple cells for transfer to an input buffer module are selected and the switching planes which the selected cells are to use in the transmission are concurrently determined.

Optical output buffered ATM switch prototype based on FRONTIERNET architecture

We constructed a rack-mounted prototype photonic ATM switch based on the FRONTIERNET architecture. The advantages of the architecture are that its output-buffering scheme overcomes the bottlenecks that can occur when receiving and storing concurrent high-speed cells, and that there is no need to deal with contention resolution between input highways. The prototype has 16 input/output ports and 2.5 Gb/s transmission speed. Actually, six input ports and one output port are mounted in two racks. We demonstrated successful cell routing and buffering, and its stable operation, with 24-h bit-error-free switching operation. We also discussed problems to be solved in increasing the throughput of FRONTIERNET.

Look-ahead reservation-based scheduling for input–output buffered ATM switch

The authors present a decentralised scheduling approach for an input–output buffered ATM switch based on look-ahead reservation that minimises head-of-line blocking. Cells in an input port are queued separately according to their destined output port. To schedule the transmission time of cells in the input buffer, the input port may send requests to output ports to reserve bandwidth and buffer space at most ω cell times in advance. The reservation request carries with it the state information of the input port which allows the output port to compute a conflict-free schedule. Co-ordination among input/output ports are not required. This approach effectively minimises head-of-line blocking. A simulation study reveals that the performance of the proposed method, in terms of throughput and cell delay, is substantially better than the windowing approach and is close to that of the optimal scheduling method using exhaustive search.

Design and performance of a threshold-based load balancing scheme in an ATM switch

We consider an ATM switch consisting of a number of output-buffered ATM switch elements operating in parallel. Such an architecture may lead to uneven distribution of cells over the parallel switch element buffers, if no modifications to the design is made. With this motivation, we propose a threshold based load balancing method to evenly distribute the cells over the parallel switch element buffers. We present the details of how the load balancing method can be implemented. Our computer simulations show that the proposed load balancing method significantly reduces the cell loss probability. The study is done with two input traffic models: random traffic and bursty traffic.

Design and analysis of a large-scale multicast output buffered ATM switch

Proposes and analyzes a recursive modular architecture for implementing a large-scale multicast output buffered ATM switch (MOBAS). A multicast knockout principle, an extension of the generalized knockout principle, is applied in constructing the MOBAS in order to reduce the hardware complexity (e.g., the number of switch elements and interconnection wires) by almost one order of magnitude. In the proposed switch architecture, four major functions of designing a multicast switch: cell replication, cell routing, cell contention resolution, and cell addressing, are all performed distributively so that a large switch size is achievable. The architecture of the MOBAS has a regular and uniform structure and, thus, has the advantages of: (1) easy expansion due to the modular structure, (2) high integration density for VLSI implementation, (3) relaxed synchronization for data and clock signals, and (4) building the center switch fabric (i.e., the multicast grouping network) with a single type of chip. A two-stage structure of the multicast output buffered ATM switch (MOBAS) is described. The performance of the switch fabric in cell loss probability is analyzed, and the numerical results are shown. The authors show that a switch designed to meet the performance requirement for unicast calls will also satisfy multicast calls' performance. A 16/spl times/16 ATM crosspoint switch chip based on the proposed architecture has been implemented using CMOS 2-/spl mu/m technology and tested to operate correctly. >

Analysis of an output-buffered ATM switch with speed-up constraints under correlated and imbalanced bursty traffic

The authors consider a discrete-time model of an access ATM switch with output buffers. A switch with output queueing has an optimum performance; however, it requires a switch fabric with speed N. However, the switch fabric may operate at L<N times the speed of the input/output links. The random traffic assumption underestimates the buffer size. Each input port of the switch is assumed to be driven by an interrupted Bernoulli process and every cell in a burst is directed to the same output port. An efficient aggregation method is applied for the performance analysis of the switch. The results prove to be very good.

Performance of various input-buffered and output-buffered ATM switch design principles under bursty traffic: simulation study

This paper investigates the packet loss probabilities of several alternative input-buffered and output-buffered switch designs with finite amounts of buffer space. The effects of bursty traffic, modeled by geometrically distributed active and idle periods, are explored. Methods for improving switch performance are classified, and their effectiveness for dealing with bursty traffic discussed. This work indicates that bursty traffic can degrade switch performance significantly and that it is difficult to alleviate the performance degradation by merely restricting the offered traffic load. Unless buffers are shared, or very large buffers provided, strategies that improve throughput under uniform random traffic are not very effective under bursty traffic. For input-buffered switches, our investigation suggests that the specific contention resolution scheme we use is a more important performance factor under bursty traffic than it is under uniform random traffic. In addition, many qualitative results true for uniform random traffic are not true for bursty traffic. The work also reveals several interesting, and perhaps unexpected, results: 1) output queueing may have higher loss probabilities than input queueing under bursty traffic; 2) speeding up the switch operation could result in worse performance than having several output ports per output address under bursty traffic; and 3) if buffers are not shared in a fair manner, sharing buffers could make performance worse than not sharing buffers at high traffic loads. Simulation results and intuitive explanations supporting the above observations are presented. >

An output-buffered ATM switch in the multichannel bandwidth allocation environment

It is desirable in the high-speed broadband communication network to satisfy the high-level requirements for the communication quality for various communication services while efficiently utilizing the communication network resources. From such a viewpoint, Pattavina proposed a multichannel bandwidth allocation scheme and constructed an input-buffered multichannel ATM switch based on the forementioned scheme. This paper follows his idea and discusses the construction of a multichannel ATM switch with buffers at both the input and the output, a well as with the buffer only at the output. A periodic channel assignment algorithm is proposed, aiming at the balanced load allocation among the channels of the same output channel group. The proposed algorithm helps to share efficiently the resources (buffer and channel) of the same output channel group and to realize an economical use of the buffer. The performance evaluation is made for the case where the buffer is provided only on the output side. It is shown as a result that the cell loss probability and the buffer size required to satisfy the specified loss probability are greatly reduced with the increase of the group size. It is shown also that a better throughput-delay performance is obtained than that of the input-buffered multichannel ATM switch.