Original Finite State Machine Research Articles

SATAM: A SAT Attack Resistant Active Metering Against IC Overbuilding

In the horizontal semiconductor business model, a foundry can tamper or overbuild the integrated circuits (ICs) while the IC owner knows nothing about it. Active IC metering scheme has been proposed to solve this problem by enabling IC owners to uniquely identify each manufactured chip. We propose a new active metering scheme, SATAM. In the scheme, a new cell of switchable scannable flip-flop (WFF) is introduced to be inserted in the non-critical paths or replace some original scan cells. Without a correct key on these WFFs, the synchronization status of the original design is violated and hence the circuit logic is locked (obfuscated). The scan design is also obfuscated by the introduction of WFFs, which helps the locking scheme to resist the typical SAT attack and other existing attacks on logic locking. To enable each fabricated chip to have a unique key to unlock, a via-based physical unclonable function (PUF) is adopted due to its perfect reliability. A new post-processing method is proposed to improve its uniqueness and randomness. Also, we propose to modify the original finite state machine (FSM) so that the PUF response can only be retrieved by the chip designer in a secure way. The experimental results show that the locking scheme based on WFFs can well resist the SAT attack and other existing attacks on logic obfuscation. The PUF design can achieve satisfactory uniqueness and randomness while incurring lower overhead. The FSM-based retrieval scheme can secure the PUF response by slightly modifying the original FSM. The overhead due to the overall metering method is smaller than most of the existing metering methods while it can resist typical attacks.

An Efficient Signature Matching Scheme for Mobile Security

SUMMARY The development of network technology reveals the clear trend that mobile devices will soon be equipped with more and more network-based functions and services. This increase also results in more intrusions and attacks on mobile devices; therefore, mobile security mechanisms are becoming indispensable. In this paper, we propose a novel signature matching scheme for mobile security. This scheme not only emphasizes a small resource requirement and an optimal scan speed, which are both important for resource-limited mobile devices, but also focuses on practical features such as stable performance, fast signature set updates and hardware implementation. This scheme is based on the finite state machine (FSM) approach widely used for string matching. An SRAM-based two-level finite state machine (TFSM) solution is introduced to utilize the unbalanced transition distribution in the original FSM to decrease the memory requirement, and to shorten the critical path of the single-FSM solution. By adjusting the boundary of the two FSMs, optimum memory usage and throughput are obtainable. The hardware circuit of our scheme is designed and evaluated by both FPGA and ASIC technology. The result of FPGA evaluation shows that 2,168 unique patterns with a total of 32,776 characters are stored in 177.75 KB SelectRAM blocks of Xilinx XC4VLX40 FPGA and a 3.0 Gbps throughput is achieved. The result of ASIC evaluation with 180 nm-CMOS library shows a throughput of over 4.5 Gbps with 132 KB of SRAM. Because of the small amount of memory and logic cell requirements, as well as the scalability of our scheme, higher performance is achieved by instantiating several signature matching engines when more resources are provided.

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

This paper presents a finite-state machine (FSM) reengineering method that enhances the FSM synthesis by reconstructing a functionally equivalent but topologically different FSM based on the optimization objective. This method enables the FSM synthesis algorithms to explore a set of functionally equivalent FSMs and obtain better solutions than those in the original FSM. To demonstrate the effectiveness of the proposed method, we apply it to popular power- and area-driven FSM synthesis algorithms, respectively. Our method achieves an average of 5.5% power reduction and 2.7% area reduction, respectively, on 25 Microelectronics Center of North Carolina (MCNC) FSM benchmarks, where the proposed method is applicable. This is a significant performance improvement for the power- and area-driven FSM synthesis algorithms being used. Our method has a negligible run-time overhead, and it maintains the quality of the synthesis solutions.

Low-power state encoding for partitioned FSMs with mixed synchronous/asynchronous state memory

Partitioned finite state machine (FSM) architectures in general enable low-power implementations and it has been shown that for these architectures, state memory based on both synchronous and asynchronous storage elements gives lower power consumption compared to their fully synchronous counterparts. In this paper we present state encoding techniques for a partitioned FSM architecture based on mixed synchronous/asynchronous state memory. The state memory, in this case, is composed of a synchronous local state memory and an asynchronous global state memory. The local state memory uses synchronous storage elements and is shared by all sub-FSMs. The global state memory operates asynchronously and is responsible for handling the interaction between sub-FSMs. Even though the partitioned FSM contains the asynchronous mechanism, its input/output behaviour is still cycle by cycle equivalent to the original monolithic synchronous FSM. In this paper, we discuss the low-power state encoding method for the implementation of partitioned FSM with mixed synchronous/asynchronous state memory. For the local state assignment a, what we call, state-bundling procedure is presented to enable states residing in different sub-FSMs to share the same state codes. Based on state-bundles, two state encoding techniques, in which one is the employment of binary encoding and the other is the further optimization for low power, are compared.

SPaRre: selective partial replication for concurrent fault-detection in FSMs

We discuss SPaRe: selective partial replication, a methodology for concurrent fault detection in finite state machine (FSMs). The proposed method is similar to duplication, wherein a replica of the circuit acts as a predictor that immediately detects errors by comparison to the original FSM. However, instead of duplicating the FSM, SPaRe selects a few prediction functions which only partially replicate it. Selection is guided by the objective of minimizing the incurred hardware overhead without compromising the ability to detect all faults, yet possibly introducing fault-detection latency. SPaRe is nonintrusive and does not interfere with the encoding and implementation of the original FSM. Experimental results indicate that SPaRe achieves significant hardware overhead reduction over both duplication and test vector logic replication (TVLR), a previously reported concurrent fault-detection method. Moreover, as compared to TVLR, SPaRe also reduces the average fault-detection latency for detecting all permanent faults.

Implicit FSM decomposition applied to low-power design

Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In this paper, we describe a clock-gating technique based on finite-state machine (FSM) decomposition. The approach is based on the computation of two sub-FSMs that together have the same functionality as the original FSM. For all the transitions within one sub-FSM, the clock for the other sub-FSM is disabled. To minimize the average switching activity, we search for a small cluster of states with high stationary state probability and use it to create the small sub-FSM. Explicit manipulation of the state transition graph requires time and space exponential on the number of registers in the circuit, thereby restricting the applicability of explicit methods to relatively small circuits. The approach we propose is based on a method that implicitly performs the FSM decomposition. Using this technique, the FSM decomposition is performed by direct manipulation of the circuit. We provide a set of experiments that show that power consumption can be substantially reduced, in some cases by more than 70%.

On optimal control of a class of partially observed discrete event systems

We are interested in a new class of optimal control problems for discrete event systems. We adopt the formalism of supervisory control theory (Proc. IEEE 77(1) (1989) 81) and model the system as a finite state machine (FSM). Our control problem is characterized by the presence of uncontrollable as well as unobservable events, the notion of occurrence and control costs for events and a worst-case objective function. We first derive an observer for the partially unobservable FSM, which allows us to construct an approximation of the unobservable trajectory costs. We then define the performance measure on this observer rather than on the original FSM itself. We then use the algorithm presented in Sengupta and Lafortune (SIAM J. Control Optim. 36(2) (1998)) to synthesize an optimal submachine of the C-observer. This submachine leads to the desired supervisor for the system.

Factorizing FSM's with modify and restore method

Implementation of large finite-state machines (FSMs) as smaller interacting machines, by factorizing them and interconnecting the factored and factoring FSM's in such a way so as to maintain the functionality of the original machine usually leads to an improvement in the performance (that is, reduction in delay) of the original machine. Exact factors, if present in an FSM, can result in the most effective way of factorization. However, it has been found that most of the FSMs are not exact factorizable. In this paper, we have presented a scheme called the modify and restore (MAR) method which attempts to make FSMs exact factorizable even if the original FSM is not directly exact factorizable. This is done by making minor changes in the next state space of the original FSM while maintaining the functionality of the FSM by a restoring logic. We have tested the effectiveness of our method of factorization followed by state assignment for both two-level and multilevel implementations. Experimental results on the MCNC benchmark examples have shown significant improvement in delays of the final realization.

Algorithms for approximate FSM traversal based on state space decomposition

This paper presents algorithms for approximate finite state machine traversal based on state space decomposition. The original finite state machine is partitioned in component submachines, and each of them is traversed separately; the result of the computation is an over-estimation of the set of reachable states of the original machine. Different traversal strategies, which reduce the effects of the degrees of freedom introduced by the decomposition, are discussed. Efficient partitioning is a key point for the performance of the traversal techniques; a method to heuristically find a good decomposition of the overall finite state machine, based on the exploration of its state variable dependency graph, is proposed. Applications of the approximate traversal methods to logic optimization of sequential circuits and behavioral verification of finite state machines are described; experimental results for such applications, together with data concerning pure traversal, are reported.