Optoelectronic Interconnection Networks Research Articles

BSN MOT: A Fast and Cost-efficient Optoelectronic Architecture

Recently, an efficient recursive and symmetrical optoelectronic interconnection network based on biswapped framework named “Biswapped-Hyper Hexa-Cell (BSN HHC)” is reported. In spite of containing a prime advantage concerning network diameter compared to its competitive Biswapped-Mesh (BSN Mesh) optoelectronic architecture; a major limitation of the network is its high cost. In a search for a competitive alternative variation of this network, a fast and a cost-efficient member of biswapped family named “Biswapped-Mesh of Trees (BSN MOT)” is proposed here. The suggested BSN MOT optoelectronic network claims to be a better alternative of counter-part OTIS-Mesh of Trees (OTIS MOT) optoelectronic network, claims advantages concerning diameter, minimum node degree, and network total and optical cost (total cost drops about 10–30% and optical cost drops about 50%). More specifically, compared to competitive Biswapped-Mesh and BSN HHC optoelectronic networks, the proposed network has a major advantage concerning network diameter. Moreover, BSN MOT is a cost-efficient architecture, where total network cost drops about 30–45% than that of BSN HHC. Besides, it is a better alternative for processing numerical problems that require network with “low static maximum node degree”. Thus, on the basis of above-mentioned properties, the proposed network claims to be the most economical and the fastest variation of biswapped framework.

The Construction of High-Performance Optoelectronic Interconnection Network and the Realization of Cloud Computing for Traffic Data Recognition

Due to the problems of congestion, insufficient scalability, and high cost in the network core layer link, the network interconnection architecture needs to be optimized. The photoelectric interconnection technology has attracted the attention of many researchers with its high bandwidth, low latency, and low power consumption. In this study, after fully considering the requirements of optoelectronic switching on network node degree and processing delay and corresponding to different transmission characteristics of circuit switching and optical circuit switching, an optoelectronic interconnection architecture supporting heterogeneous network topology, namely THtop, is proposed. According to the optical circuit switching/circuit switching characteristics of the Internet, the corresponding topology structure is designed respectively in this architecture to enhance the system integration and reduce the cost. At the same time, in order to meet the requirements of wavelength and number of hops of optical circuit switching, distributed control is designed in THtop, and the design method of heterogeneous optical switching unit is introduced in the switching equipment, so that the optical switching node can further reduce the cost while playing its role. The use of high-speed optoelectronic networks will cause a large amount of traffic on the channel. In this study, the traffic identification is analyzed on the proposed THtop architecture. The Map Reduce framework in cloud computing is used as the identification model, and the K-means algorithm is taken as the identification algorithm. According to its characteristics, the W_K-means algorithm is proposed for the type identification of traffic. The results show that under the OpenNet Internet simulation environment, when the traffic is set to a certain level, more than 90% of the non-blocking network switching can be realized under the THtop architecture, and the completion time of the mouse flow and elephant flow can be significantly improved. Therefore, under the Map Reduce model, the proposed W_K -means algorithm can quickly identify different traffic types.

Factor‐Optical‐Factor Exchanges Method: a new load balancing method for Extended Optical Transpose Interconnection System‐n‐Cube networks

SummaryThe Optical Transpose Interconnection System (OTIS) optoelectronic interconnection network architecture is a promising attraction in the new era of parallel computing topologies because of its attractive topological properties. Recently, many enhancements were presented on OTIS topologies including the Extended OTIS‐n‐Cube interconnection networks. Therefore, all performance improvement characteristics of such a promising architecture need to be investigated; one of which is load balancing technique. This paper focuses on developing an efficient algorithm for load balancing on the promising Extended OTIS‐n‐Cube interconnection networks. The proposed algorithm is called Factor‐Optical‐Factor Exchange Model. Furthermore, this paper presents theoretical and experimental study on the proposed algorithm in terms of various parameters including execution time, load balancing accuracy, number of communication steps, and speed. Results show superiority of the proposed algorithm over the well‐known Clustered Dimension Exchange Method (CDEM) algorithm in terms of execution time, number of communication steps, and speed, while maintaining the same level of accuracy. Copyright © 2015 John Wiley & Sons, Ltd.

Physical models and algorithms for optoelectronic MCM layout

Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over "long" distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGHs) are extremely attractive optical components for use in free space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGHs for general interconnection networks require the need for placement algorithms for large processing element (PEs) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGHs for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnects in parallel optoelectronic MCM systems are then identified from which we derive several logical models for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Locality-based control algorithms for reconfigurable optical interconnection networks

Hybrid optoelectronic computing structures are required for providing the information processing capabilities for the next generation of computing and communications systems. Reconfigurable optoelectronic interconnection networks are networks constructed of optical waveguides in which messages are switched or routed by means of optoelectronic devices. For these networks, the dichotomy between the bandwidth of the optical channels that carry messages and the performance of the electronic controllers and decoders that determine the routing and destination of those messages is a significant bottleneck. We introduce a class of routing algorithms for reconfigurable networks that is designed to bridge this gap in optical versus electronic performance. The algorithms are based on a new control paradigm that exploits the locality in multiprocessor communication streams to reduce the control latency inherent in reconfigurable interconnection structures. In addition, we show that this problem maps directly to the problem of page replacement in a virtual-memory hierarchy. Thus our solution is well suited to networks for multiprocessor applications.

Grain-size considerations for optoelectronic multistage interconnection networks

This paper investigates, at the system level, the performance-cost trade-off between optical and electronic interconnects in an optoelectronic interconnection network. The specific system considered is a packet-switched, free-space optoelectronic shuffle-exchange multistage interconnection network (MIN). System bandwidth is used as the performance measure, while system area, system power, and system volume constitute the cost measures. A detailed design and analysis of a two-dimensional (2-D) optoelectronic shuffle-exchange routing network with variable grain size K is presented. The architecture permits the conventional 2 x 2 switches or grains to be generalized to larger K x K grain sizes by replacing optical interconnects with electronic wires without affecting the functionality of the system. Thus the system consists of log(k) N optoelectronic stages interconnected with free-space K-shuffles. When K = N, the MIN consists of a single electronic stage with optical input-output. The system design use an effi ient 2-D VLSI layout and a single diffractive optical element between stages to provide the 2-D K-shuffle interconnection. Results indicate that there is an optimum range of grain sizes that provides the best performance per cost. For the specific VLSI/GaAs multiple quantum well technology and system architecture considered, grain sizes larger than 256 x 256 result in a reduced performance, while grain sizes smaller than 16 x 16 have a high cost. For a network with 4096 channels, the useful range of grain sizes corresponds to approximately 250-400 electronic transistors per optical input-output channel. The effect of varying certain technology parameters such as the number of hologram phase levels, the modulator driving voltage, the minimum detectable power, and VLSI minimum feature size on the optimum grain-size system is studied. For instance, results show that using four phase levels for the interconnection hologram is a good compromise for the cost functions mentioned above. As VLSI minimum feature sizes decrease, the optimum grain size increases, whereas, if optical interconnect performance in terms of the detector power or modulator driving voltage requirements improves, the optimum grain size may be reduced. Finally, several architectural modifications to the system, such as K x K contention-free switches and sorting networks, are investigated and optimized for grain size. Results indicate that system bandwidth can be increased, but at the price of reduced performance/cost. The optoelectronic MIN architectures considered thus provide a broad range of performance/cost alternatives and offer a superior performance over purely electronic MIN's.

Optically powered arrays for optoelectronic interconnection networks

We describe a novel integrated, optically powered optoelectronic array for use in 2-D interconnection networks. We discuss a generic optoelectronic processing structure and propose two circuit schemes for realizing these interconnect arrays. It is shown that optical powering of the array pixel electronics considerably reduces the high frequency crosstalk between adjacent array elements, leading to improvements in bandwidth by >1 order of magnitude when compared with similar conventionally powered systems. Design criteria are established for determining the trade-offs between fanout and power dissipation, and factors limiting packing density in the optically powered scheme are also discussed. We also compare the performance of optically powered optoelectronic, conventional optoelectronic and all-optical systems on the basis of bandwidth, crosstalk, packing density, and functionality and find that optical powering has several advantages for use in advanced system architectures.