Optimal Datapath Research Articles

Autonomous Underwater Vehicle: 5G Network Design and Simulation Based on Mimetic Technique Control System

The Internet of Underwater Things (IoUT) exhibits promising advancement with underwater acoustic wireless network communication (UWSN). Conventionally, IoUT has been utilized for the offshore monitoring and exploration of the environment within the underwater region. The data exchange between the IoUT has been performed with the 5G enabled-communication to establish the connection with the futuristic underwater monitoring. However, the acoustic waves in underwater communication are subjected to longer propagation delay and higher transmission energy. To overcome those issues autonomous underwater vehicle (AUV) is implemented for the data collection and routing based on cluster formation. This paper developed a memetic algorithm-based AUV monitoring system for the underwater environment. The proposed Autonomous 5G Memetic (A5GMEMETIC) model performs the data collection and transmission to increase the USAN performance. The A5GMEMETIC model data collection through the dynamic unaware clustering model minimizes energy consumption. The A5GMemetic optimizes the location of the nodes in the underwater environment for the optimal data path estimation for the data transmission in the network. Simulation analysis is performed comparatively with the proposed A5Gmemetic with the conventional AEDG, DGS, and HAMA models. The comparative analysis expressed that the proposed A5GMeMEMETIC model exhibits the ~12% increased packet delivery ratio (PDR), ~9% reduced delay and ~8% improved network lifetime.

Optimal Architecture of Floating-Point Arithmetic for Neural Network Training Processors.

The convergence of artificial intelligence (AI) is one of the critical technologies in the recent fourth industrial revolution. The AIoT (Artificial Intelligence Internet of Things) is expected to be a solution that aids rapid and secure data processing. While the success of AIoT demanded low-power neural network processors, most of the recent research has been focused on accelerator designs only for inference. The growing interest in self-supervised and semi-supervised learning now calls for processors offloading the training process in addition to the inference process. Incorporating training with high accuracy goals requires the use of floating-point operators. The higher precision floating-point arithmetic architectures in neural networks tend to consume a large area and energy. Consequently, an energy-efficient/compact accelerator is required. The proposed architecture incorporates training in 32 bits, 24 bits, 16 bits, and mixed precisions to find the optimal floating-point format for low power and smaller-sized edge device. The proposed accelerator engines have been verified on FPGA for both inference and training of the MNIST image dataset. The combination of 24-bit custom FP format with 16-bit Brain FP has achieved an accuracy of more than 93%. ASIC implementation of this optimized mixed-precision accelerator using TSMC 65nm reveals an active area of 1.036 × 1.036 mm2 and energy consumption of 4.445 µJ per training of one image. Compared with 32-bit architecture, the size and the energy are reduced by 4.7 and 3.91 times, respectively. Therefore, the CNN structure using floating-point numbers with an optimized data path will significantly contribute to developing the AIoT field that requires a small area, low energy, and high accuracy.

Design of Precise Multiplier Using Inexact Compressor for Digital Signal Processing

In the recent years, error recovery circuits in optimized data path units are adopted with approximate computing methodology. In this paper the novel multipliers have effective utilization in the newly proposed two different 4:2 approximate compressors that generate Error free Sum (ES) and Error free Carry (EC). Proposed ES and Proposed EC in 4:2 compressors are used for performing Partial Product (PP) compression. The structural arrangement utilizes Dadda structure based PP. Due to the regularity of PP arrangement Dadda multiplier is chosen for compressor implementation that favors easy standard cell ASIC design. In this, the proposed compression idealogy are more effective in the smallest n columns, and the accurate compressor in the remaining most significant columns. This limits the error in the multiplier output to be not more than 2n for an n X n multiplication. The choice among the proposed compressors is decided based on the significance of the sum and carry signals on the multiplier result. As an enhancement to the proposed multiplier, we introduce two Area Efficient (AE) variants viz., Proposed-AE (P-AE), and P-AE with Error Recovery (P-AEER). The proposed basic P-AE, and P-AEER designs exhibit 46.7%, 52.9%, and 52.7% PDP reduction respectively when compared to an approximate multiplier of minimal error type and are designed with 90nm ASIC technology. The proposed design and their performance validation are done by using Cadence Encounter. The performance evaluations are carried out using cadence encounter with 90nm ASIC technology. The proposed-basic P-AEA and P-AEER designs demonstrate 46.7%, 52.9% and 52.7% PDP reduction compared to the minimal error approximate multiplier. The proposed multiplier is implemented in digital image processing which revealed 0.9810 Structural SIMilarity Index (SSIM), to the least, and less than 3% deviation in ECG signal processing application.

Risk-aware optimized quickest path computing technique for critical routing services

In this paper, a novel model has been proposed for the computation of optimized path with link reliability, delay and capacity. Algorithms have been proposed for the optimized data path with a single link-weight and it constitutes two main parts: (i) characterization of the network for the best optimized path, and (ii) tuning of the network parameters for the prediction/validation for the Best Optimized Path, according to a given data flow. It also needs very little a priori information during the online computation as the computed optimized path requires less computational overhead as each data flow shall be assigned with a precomputed and optimized link weight. Now, with the help of this optimized link weight one can find the optimum path with respect to both risk and lag-time in an online approach simply by adopting the Dijkstra's algorithm. This approach has been illustrated here in this paper with the help of two different topologies for different values of data flow from single source to single destination. Algorithms have been proposed based on this mathematical model. It also can be observed that proposed algorithms are able to compute the optimized path with having complexity of Dijkstra's algorithm when computer together. This study can be claimed that the proposed algorithms are self-sufficient to provide the risk-aware quickest path routing, even without having any prior information on the path to be allocated. One can easily extend it for the case of many source nodes to the many destination nodes as well as for the software defined networking (SDN) in the future work.

Analytical modelling solution of producer mobility support scheme for named data networking

Named Data Networking (NDN) is a clean-slate future Internet architecture proposed to support content mobility. However, content producer mobility is not supported fundamentally and faces many challenges such as, high handoff latency, signaling overhead cost and unnecessary Interest packet losses. Hence, many approaches indirection-based approach, mapping-based approach, locator-based approach and control/data plane-based approach were proposed to address these problems. Mapping-based and control/data plane-based approach deployed servers for name resolution serveces to provide optimal data path after handoff, but introduces high handoff latency and signalling overhead cost. Indirection-based and locator-based approach schemes provide normal handoff delay, but introduces sub-optimal or tiangular routing path. Therefore, there is needs to provide substantial producer mobility support that minimizes the handoff latency, signaling cost and improve data packets delivery via optimal path once a content producer relocates to new location. This paper proposed a scheme that provides optimal data path using mobility Interest packets and broadcasting strategy. Analytical investigation result shows that our proposed scheme outperforms existing approaches in terms of handoff latency, signaling cost and path optimization.

Mobile-Oriented Future Internet: Implementation and Experimentations over EU–Korea Testbed

Today’s mobility management (MM) architectures, such as Mobile Internet Protocol (IP) and Proxy Mobile IP, feature integration of data and control planes, as well as centralized mobility control. In the existing architecture, however, the tight integration of the data and control planes can induce a non-optimal routing path, because data packets are delivered via a central mobility agent, such as Home Agent and Local Mobility Anchor. Furthermore, the centralized mobility control mechanism tends to increase traffic overhead due to the processing of both data and control packets at a central agent. To address these problems, a new Internet architecture for the future mobile network was proposed, named Mobile-Oriented Future Internet (MOFI). The MOFI architecture was mainly designed as follows: (1) separation of data and control planes for getting an optimal data path; (2) distributed identifier–locator mapping control for alleviating traffic overhead at a central agent. In this article, we investigate the validity of the MOFI architecture through implementation and experimentations over the European Union (EU)–Korea testbed network. For this purpose, the MOFI architecture is implemented using OpenFlow and Click Modular Router over a Linux platform, and then it is evaluated over the locally and internationally configured EU–Korea testbed network. In particular, we operate two realistic communication scenarios over the EU–Korea testbed network. From the experimentation results, we can see that the proposed MOFI architecture can not only provide the mobility management efficiently, but also support the backward compatibility for the current IP version 6 (IPv6) applications and an Internet Protocol network.

S2VC: An SDN-based framework for maximizing QoE in SVC-based HTTP adaptive streaming

HTTP adaptive streaming (HAS) is quickly becoming the dominant video delivery technique for adaptive streaming over the Internet. Still considered as its primary challenges are determining the optimal rate adaptation and improving both the quality of experience (QoE) and QoE-fairness. Most of the proposed approaches have relied on local information to find a result. However, employing techniques that provide a comprehensive and central view of the network resources can lead to more gains in performance. By leveraging software defined networking (SDN), this paper proposes an SDN-based framework, named S2VC, to maximize QoE metrics and QoE-fairness in SVC-based HTTP adaptive streaming. The proposed framework determines both the optimal adaptation and data paths for delivering the requested video files from HTTP-media servers to DASH clients. In fact, by utilizing an SDN controller and its complete view of the network, we introduce an SVC flow optimizer (SFO) application module to determine the optimal solution in a centralized and time slot fashion. In the current approach, we first formulate the problem as a mixed integer linear programming (MILP) optimization model. The MILP is designed in such a way that it applies defined policies, e.g. setting priorities for clients in obtaining video quality. Secondly, we show that this problem is NP-complete and propose an LP-relaxation model to enable S2VC framework for performing rate adaptation on a large-scale network. Finally, we conduct experiments by emulating the proposed framework in Mininet, with the usage of Floodlight as the SDN controller. In terms of improving QoE-fairness and QoE metrics, the effectiveness of the proposed framework is validated by a comparison with different approaches.

Improvements for DMM in SDN and Virtualization Based Mobile Network Architecture

The (r)evolution of wireless access infrastructure can be described as the convergence of the available radio communication systems towards a harmonized, more flexible and reconfigurable access system to match the current and upcoming demands. In recent years Softwarization and Virtualization technologies have moved from server and network domains to wireless domain and provides new perspectives of managing mobile networks functionalities. This paper provides evolution of the mobile network architecture in Software Defined Networking (SDN) and virtualization context and realizes it through the use of distribution of gateway function approach. Key improvements with proposed approach are to support efficient mobility management in heterogeneous access environments, remove the chains of IP preservation and optimal data path management according to application needs. A functional setup validates and assays the proposed evolution in terms of inter-system handover preparation, interruption and completion time relative to control plane delay requirements of the 5G networks.

Asynchronous carry select adders

This paper discusses the standard cell based designs of asynchronous carry select adders (CSLAs) corresponding to strong-indication, weak-indication, and early output timing regimes realized using a delay-insensitive dual-rail code for data representation and processing, and a 4-phase return-to-zero protocol for handshaking. Many 32-bit asynchronous CSLAs corresponding to a uniform input partition viz. 8-8-8-8 and a non-uniform input partition viz. 8-7-6-4-3-2-2 were considered for implementation and comparison. All the asynchronous CSLAs were physically realized in semi-custom ASIC design style using a 32/28nm CMOS process technology. The simulation results show that the 32-bit early output asynchronous CSLA based on the uniform input partition (8-8-8-8) enables optimized data path latency, area occupancy, and average power dissipation compared to the rest.

Multihop data gathering in wireless sensor networks with a mobile sink

SummaryNetwork performance can be improved by using a mobile sink (MS) to collect sensed data in a wireless sensor network. In this paper, we design an efficient trajectory for MS, collecting data from sensor nodes in a multihop fashion, with the aim of prolonging the network lifetime. Considering event‐driven applications, we present an approach to jointly determine the optimal trajectory for MS and data paths and transmission rates from source nodes to MS, without considering any rendezvous points. In these applications, an MS is supposed to harvest the data from source nodes in a given time‐slot. We first show that this problem is in form of a mixed integer nonlinear programming model, which is NP‐hard. Then, to achieve an approximate solution, we divide the mentioned problem into 2 simple subproblems. In fact, after determining an approximate zone for the trajectory of MS, the optimal data paths and transmission rates from source nodes to the MS are obtained through a mathematical optimization model. Finally, to illustrate the efficiency of the proposed approach, we compare the performance of our algorithm to an rendezvous point–based and also the state‐of‐the‐art approach in different scenarios.

Optimal Placement of Cellular Transceiver for Transmission Line Monitoring Using Genetic Algorithm

In recent decades, automation and modernization inhabit a vital role in the electric power industry. For reliable operation, the transmission network has to be continuously monitored and smarter decisions could be executed to satisfy the real time needs. In this respect, electrical transmission towers are installed with wireless sensor network (WSN) to gather the information from the transmission line network. The collected information is transmitted to the control centre for further actions through hybrid hierarchical network architecture. The hybrid architecture consists of a combination of wired, wireless and cellular technologies. WSNs are facing the bottleneck problem during transmission of data due to the bandwidth and latency of low data rate devices. Installation of cellular transceiver in transmission towers can reduce bottleneck problems remarkably. Whereas the installation of cellular transceivers cause high cost. Hence, this paper explains the optimistic ways for optimal placement of cellular transceivers with minimum cost. The objective is to define cellular node locations in order to improve network performance in terms of bandwidth and end-to-end delay. To attain the cost optimistic location of cellular transceivers, a heuristic algorithm based on genetic strategy is developed and applied to a benchmark set of problems. Experiments by simulations are conducted to evaluate the performance of the proposed algorithm in this paper. Model solutions specify both where to place the cellular transceivers and the optimal data paths to route the data. The optimization problem is carried with the objective of minimizing the installation cost. Through a comprehensive evaluation in simulation we show that our approach is effective in accomplishing the desired objectives for corridor of several hundreds of towers.

Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency

Datapath widths in state-of-the-art Turbo and Viterbi decoder implementations depend on estimated upper bounds of the differences of processed metrics. Aiming at highest area and energy efficiency,...

Simultaneous exploration of optimal datapath and loop based high level transformation during area-delay tradeoff in architectural synthesis using swarm intelligence

This paper presents the first transformation methodology of a swarm intelligence algorithm into design space exploration (DSE) of optimal datapath and unrolling factor during area-performance tradeoff in high level synthesis (HLS). To the best of the authors’ belief, in the literature, the above transformation has not been performed so far for developing a fully automated integrated exploration methodology of optimal datapath and unrolling factor. DSE problem being intractable and complex in the presence of auxiliary variable such as loop unrolling factor requires administration of intelligent decision making strategies at multiple stages to yield optimal results. The major sub-contributions of this proposed algorithm includes: a) Deriving a model for execution delay computation of a loop unrolled control data flow graph (CDFG) based on available resources, b) handling area-execution delay tradeoff during our integrated DSE process; c) Sensitivity analysis of particle swarm optimization (PSO) parameters used in assisting the designer in pre-tuning the baseline parameters during final area-performance tradeoff. Results of the proposed approach indicated an average improvement in Quality of Results (QoR) of > 23% and reduction in runtime of > 92% compared to recent approaches.

A solution for transparent mobility with route optimization in the IP multimedia subsystem

This paper presents TRIM+, an architecture for transparent mobility management with route optimization in IMS based networks. The design of our architecture is based on a previous work referred to as TRIM. TRIM was originally devised to provide transparent mobility support in the IMS, although transparency came at the cost of using a suboptimal data path between communicating end points. TRIM+ maintains transparency as a design criterium, and thus end-user applications, running at the mobile node and its correspondent communication peers, are unaware of mobility management procedures. Additionally, the proposed design defines a set of route optimization procedures, allowing compliant devices to use the optimal data path for media communications. Furthermore, TRIM+ addresses packet loss management in scenarios where the media path cannot be maintained during the handover of the MN. To this end, our architecture enables the MN to request buffering capacity in its home network to temporarily store incoming media traffic during the handover, which would otherwise be dropped. This mechanism, as well as route optimization procedures, are executed transparently to the end-user applications running at the communicating end points. As a proof-of-concept, we have implemented a software prototype of the TRIM+ architecture, deploying it over a real IMS testbed. By means of a set of experiments, we have validated the mechanisms proposed in this paper, considering both UDP and TCP user traffic.

Binding Query를 활용한 Proxy Mobile IPv6의 성능 향상 기법

Proxy Mobile IPv6 (PMIPv6) 프로토콜에서는 단말간 통신 시에 모든 데이터 패킷이 Local Mobility Anchor (LMA)를 거쳐 전달되어 통신단말이 모두 동일 망에 위치한 경우 데이터 패킷이 최적화되지 않은 경로를 사용함으로 인해 성능이 저하된다. 본 논문에서는 Binding Query를 활용한 PMIPv6의 경로최적화 기법을 제안한다. 제안되는 Query-based PMIPv6 (Q-PMIPv6) 기법에서 Correspondent Node (CN)의 Mobile Access Gateway (MAG)는 Mobile Node (MN)의 Proxy Care-of-Address를 획득하기 위하여 LMA로 Binding Query를 보내고, 이후에 CN과 MN는 최적화된 경로를 이용하여 데이터 전송을 수행한다. 성능분석을 위해 제안하는 Q-PMIPv6 기법과 기존의 PMIPv6 및 PMIPv6 Localized Routing (PMIPv6-LR) 기법을 이론적인 수치 분석 및 ns-2 시뮬레이션을 통해 비교하였다. 비교 분석 결과, 제안하는 Q-PMIPv6 기법이 시그널링 비용 및 데이터 전달 비용 측면에 서 기존 PMIPv6 및 PMIPv6-LR 기법에 비해 우수함을 확인하였다. In the Proxy Mobile IPv6 (PMIPv6), the data transmission performance may be degraded when the two communicating hosts are located within the same mobile domain, since all the data packet shall be delivered by way of Local Mobility Anchor (LMA). In this paper we propose an extensional scheme of PMIPv6 using binding query. In the proposed Query-based PMIPv6 (Q-PMIPv6) scheme, the Mobile Access Gateway (NAG) of Correspondent Node (CN) sends a binding query to LMA to obtain the Proxy Care-of-Address of Mobile Node (MN). Since then, CN and MN can communicate with each other by using an optimized data path. For comparison, we performed the numerical analysis and the ns-2 simulations for the proposed Q-PMIPv6 scheme and the existing PMIPv6 and PMIPv6 Localized Routing (PMIPv6-LR). From the results, we can see that the proposed scheme outperforms the existing PMIPv6 and PMIPv6-LR schemes in terms of the signaling control and data delivery costs.

A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches

In this paper, a power efficient vertex processor for mobile graphics applications is presented. A four-threaded and four-issue expanded VLIW datapath with a quad-float vertex texture fetcher is proposed by exploiting graphics specific characteristics after evaluation of several candidate architectures. Instruction-level power control methods such as operand sharing and writeback re-allocation along with operand isolations and gated clocks result in 40.4% and 82% reduction in energy dissipation and energy delay product compared to the most widely used single threaded SIMD. The proposed processor with the optimized datapath and vertex caches implemented in a 0.18- mum 1P4M CMOS process achieves 186-Mvertices/s geometry performance which is the best result among the processors that are IEEE-754 compliant.

Optimal datapath allocation for multiple-wordlength systems

High-level synthesis for multiple-wordlength systems is examined. A formulation of the combined scheduling, binding, and wordlength selection problem is proposed. Integer linear programming is used to obtain area-optimal scheduling, binding and wordlength selection for such systems.

Datapath layout optimisation using genetic algorithm and simulated annealing

The paper deals with the minimisation of the track density and the interconnection delay in the design of a high-performance compact datapath. The authors applied a hybrid approach of genetic algorithm (GA) and simulated annealing (SA) to determine the optimal datapath element ordering to minimise both the track density and the wire length. To improve the computation speed, they used the datapath-specific genetic operators. Experimental results for the ‘real-world’ microprocessor examples show that the GA/SA hybrid approach outperforms the existing genetic approaches and gives similar results to simulated annealing with much less computation time.

Design and implementation of the ‘Tiny RISC’ microprocessor

This paper describes the design and implementation of ‘Tiny RISC’, a 16-bit RISC-style microprocessor designed at UC Irvine. It was fabricated by MOSIS in a 2 μm n-well CMOS technology. Tiny RISC has been designed for optimized data path operation. A simple 32-bit extension of the data path results in a generic functional unit of a VLIW (very long instruction word) processor that is currently being developed at UC Irvine.