Optimal Register Allocation Research Articles

A novel semi-folded parallel successive cancellation-based polar decoder for optimal-register allocation

Efficient compression and reliable data transmission are the major areas in the information theory that governs various applications in mobile communication, Internets and modern digital technology. The exploitation of data patterns and redundancies offers better compression without loss of user information. The trade-off between the storage and the quality is the major requirement to apply the coding scheme in very large-scale integration. Alternatively, the reliable transmission in the presence of noise requires the prior addition of redundancy to the data. Polar codes are the practical codes suitable for channel coding and optimal performance achievement under lossy compression and complexity-based communication environment. This paper focuses on the novel architecture of successive cancellation (SC)-based polar decoding for an effective communication. The coefficient weight computation during the register update consumes a number of components in traditional SC decoding architectures. This paper proposes the semi-folded parallel successive cancellation (SFPSC) algorithm that modifies the coefficient weight computation process for register update resulting in a 4-folded polar decoding architecture to retrieve the information from the transmitted symbols with reduced resource utilization. The performance characteristics of SFPSC algorithm based on FPGA implementation are presented. The decoder architecture based on SFPSC algorithm achieves an efficient resource utilization. The reduction in a number of components efficiently reduces the time consumption. The comparative analysis between the SFPSC-based decoder with the existing SC schemes regarding the number of look up tables, FFs and memory assures the effectiveness of SFPSC in resource utilization.

The complexity of register allocation

In compilers, register allocation is one of the most important stages with respect to optimization for typical goals, such as code size, code speed, or energy efficiency. Graph theoretically, optimal register allocation is the problem of finding a maximum weight r-colorable induced subgraph in the conflict graph of a given program. The parameter r is the number of registers.Large classes of programs are structured, i.e. their control-flow graphs have bounded tree-width (Thorup (1998) [17], Gustedt et al. (2002) [8] and Burgstaller et al. (2004) [3]). The decision problem of deciding if a conflict graph of a structured program is r-colorable is known to be fixed-parameter tractable (Bodlaender et al. (1998) [1]). Optimal register allocation for structured programs is known to be in XP (Krause (2013) [13]).We complement these results by showing that optimal register allocation parametrized by r is W[SAT]-hard. This even holds for programs using only if/else and while as control structures; these programs form are subclass of the structured programs.

Optimal register allocation for SSA-form programs in polynomial time

This paper gives a constructive proof that the register allocation problem for a uniform register set is solvable in polynomial time for SSA-form programs.

Optimal register allocation for SSA-form programs in polynomial time

This paper gives a constructive proof that the register allocation problem for a uniform register set is solvable in polynomial time for SSA-form programs.

Iterative-free program analysis

Program analysis is the heart of modern compilers. Most control flow analyses are reduced to the problem of finding a fixed point in a certain transition system, and such fixed point is commonly computed through an iterative procedure that repeats tracing until convergence.This paper proposes a new method to analyze programs through recursive graph traversals instead of iterative procedures, based on the fact that most programs (without spaghetti GOTO) have well-structured control flow graphs, graphs with bounded tree width . Our main techniques are; an algebraic construction of a control flow graph, called SP Term , which enables control flow analysis to be defined in a natural recursive form, and the Optimization Theorem , which enables us to compute optimal solution by dynamic programming.We illustrate our method with two examples; dead code detection and register allocation. Different from the traditional standard iterative solution, our dead code detection is described as a simple combination of bottom-up and top-down traversals on SP Term. Register allocation is more interesting, as it further requires optimality of the result. We show how the Optimization Theorem on SP Terms works to find an optimal register allocation as a certain dynamic programming.

Optimal and Near-optimal Global Register Allocation Using 0-1 Integer Programming

This paper presents a fundamentally new approach to global register allocation that optimally allocates registers and optimally places spill code, significantly decreasing spill code overhead compared with the traditional graph-coloring approach. The Optimal Register Allocation (ORA) approach formulates global register allocation as a 0–1 integer programming problem, incorporating all aspects of register allocation within a unified framework, including copy elimination, live range splitting, rematerialization, callee and caller register spilling, special instruction-operand requirements, and paired registers. A prototype ORA allocator is built into the Gnu C Compiler (GCC). For the SPEC92 integer benchmarks, the ORA allocator actually produces a net decrease of more than 100 million cycles across the entire benchmark set, because the dynamic copies the ORA allocator removes exceed the dynamic loads and stores that are inserted. In contrast, the GCC allocator and a Chaitin-style graph-coloring allocator each cause a net increase of more than 1 billion cycles. Because global register allocation is NP-complete, optimal register allocation has been considered intractable. However, the run-time complexity of the ORA approach is shown experimentally to be O(n3). A profile-guided hybrid allocation approach is proposed that uses the ORA allocator for the performance critical regions in the performance critical functions, while using a graph-coloring allocator for the non-critical functions and regions. An ORA-GCC hybrid allocator takes an average of 4.6 seconds per function to produce an allocation that is within 1% of optimal for 97% of the SPEC92 integer benchmark functions, showing that the hybrid allocator is practical as an advanced optimization for performance-critical codes.

Optimal and Near‐optimal Global Register Allocation Using 0-1 Integer Programming

This paper presents a fundamentally new approach to global register allocation that optimally allocates registers and optimally places spill code, significantly decreasing spill code overhead compared with the traditional graph-coloring approach. The Optimal Register Allocation (ORA) approach formulates global register allocation as a 0–1 integer programming problem, incorporating all aspects of register allocation within a unified framework, including copy elimination, live range splitting, rematerialization, callee and caller register spilling, special instruction-operand requirements, and paired registers. A prototype ORA allocator is built into the Gnu C Compiler (GCC). For the SPEC92 integer benchmarks, the ORA allocator actually produces a net decrease of more than 100 million cycles across the entire benchmark set, because the dynamic copies the ORA allocator removes exceed the dynamic loads and stores that are inserted. In contrast, the GCC allocator and a Chaitin-style graph-coloring allocator each cause a net increase of more than 1 billion cycles. Because global register allocation is NP-complete, optimal register allocation has been considered intractable. However, the run-time complexity of the ORA approach is shown experimentally to be O(n3). A profile-guided hybrid allocation approach is proposed that uses the ORA allocator for the performance critical regions in the performance critical functions, while using a graph-coloring allocator for the non-critical functions and regions. An ORA-GCC hybrid allocator takes an average of 4.6 seconds per function to produce an allocation that is within 1% of optimal for 97% of the SPEC92 integer benchmark functions, showing that the hybrid allocator is practical as an advanced optimization for performance-critical codes.

Register allocation with instruction scheduling

We present a new framework in which considerations of both register allocation and instruction scheduling can be applied uniformly and simultaneously. In this framework an optimal coloring of a graph, called the parallel interference graph , provides an optimal register allocation and preserves the property that no false dependences are introduced, thus all the options for parallelism are kept for the scheduler to handle. For this framework we provide heuristics for trading off parallel scheduling with register spilling.

Heuristic algorithms for register allocation

A model to find the optimal register allocation of program variables, including large strongly connected regions (loops), is presented. The program is represented by a directed control flow graph and assumes that all variables have been allocated to memory locations. The model takes into account the cost and saving times involved in allocating variables to registers in each node of the program in order to maximise the global time saving in program execution. As the solution of this model requires exponential resources (both time and space) in the worse case, two heuristic algorithms with O(m) and O(m/sup 2/) complexities have been developed. Comparisons between the performance of the two heuristic algorithms and the optimal one are made for a set of representative programs. >

Dynamic programming for computer register allocation

A procedure for optimal index register allocation in loops is described. The procedure is a result of the dynamic programming formulation of the index register allocation problem for other than straightline code. An example involving a simple loop is solved.