Optimal Number Of Processing Elements Research Articles

Balancing EC‐Earth3 Improving the Performance of EC‐Earth CMIP6 Configurations by Minimizing the Coupling Cost

AbstractEarth System Models (ESMs) are complex systems used in weather and climate studies generally built from different independent components responsible for simulating a specific realm (ocean, atmosphere, biosphere, etc.). To replicate the interactions between these processes, ESMs typically use coupling libraries that manage the synchronization and field exchanges between the individual components, which run in parallel as a Multi‐Program, Multiple‐Data application. As ESMs get more complex (increase in resolution, number of components, configurations, etc.), achieving the best performance when running in High‐performance Computing platforms has become increasingly challenging and of major concern. One of the critical bottlenecks is the load‐imbalance, where the fastest components will have to wait for the slower ones. Finding the optimal number of processing elements to assign to each of the multiple independent constituents to minimize the performance loss due to synchronizations and maximize the overall parallel efficiency is impossible without the right performance metrics, methodology, and tools. This paper presents the results of balancing multiple Coupled Model Intercomparison Project phase 6 configurations for the EC‐Earth3 ESM. We will show that intuitive approaches can lead to suboptimal resource allocations and propose new setups up to 25% fasters while reducing the computational cost by 72%. We prove that new methods are needed to deal with the load‐balance of ESMs and hope that our study will serve as a guide to optimize any other coupled system.

Hexagonal arrays for fault-tolerant matrix multiplication

This paper describes mathematical procedure for designing hexagonal systolic arrays that implement fault-tolerant matrix multiplication. Fault-tolerance is achieved by introducing redundancy at algorithm level by defining three equivalent algorithms with disjoint index spaces. The essence of the proposed method is based on mapping data dependency graph that corresponds to the matrix multiplication algorithm, by an appropriate epimorphism, into a graph with desired properties. Since there is a 1:1 correspondence between the algorithm and it?s graph representation, all transformations performed on the graph directly affect the algorithm. Chosen epimorphism depends on the projection direction vector ?? = [?1 ?2 ?3]T and enables obtaining hexagonal arrays with optimal number of processing elements (PEs) for the given matrix dimensions, which realizes fault-tolerant matrix multiplication for the shortest possible time for that number of PEs. The proposed procedure is formally described by explicit formulas and can be used as a software tool for automatic synthesis of fault-tolerant arrays.

A class of fault-tolerant systolic arrays for matrix multiplication

This paper presents a proposal for a systematic approach for designing one class of fault-tolerant systolic arrays with orthogonal interconnects and unidirectional data flow (OUSA) for multiplication of rectangular matrices. The method employs space-time redundancy to achieve fault-tolerance. It consists of four steps. In the first step the inner computation space of the basic systolic algorithm for matrix multiplication is expanded. In the second step we derive a matrix multiplication algorithm which enables us to obtain OUSAs with data pipeline period λ = 3 . During the third step redundancy is introduced by deriving three equivalent algorithms with disjoint index spaces. In the last step the obtained algorithm is mapped into a processor-time domain. In this way we have obtained four different OUSAs. For the given matrix dimensions, two out of four arrays have an optimal number of processing elements (PEs) and minimal execution time. For the square case, all arrays have an optimal number of PEs, Ω = n ( n + 2 ) , and total execution time of T t o t = 6 n . All of them can tolerate single transient errors and the majority of multiple error patterns with high probability. In addition, two arrays can tolerate permanent faults as well. The obtained arrays are suitable for implementation in VLSI technology. Compared to a hexagonal array of the same dimensions, the number of I/O pins is reduced by approximately 30%.

Finding minimum cost spanning tree on bidirectional linear systolic array

In this paper a bidirectional linear systolic array (BLSA) that computes minimum cost spanning tree (MCST) of a given graph is designed. We present a synthesis procedure, based on data dependencies and space-time transformations of index space, to design BLSA with optimal number of processing elements (PEs) for a given problem size. The execution time is minimized for that number of PEs. Explicit mathematical formulas for systolic array synthesis are derived. We compare performances of the BLSA with the unidirectional linear systolic array (ULSA). .

Synthesis of space optimal systolic arrays for band matrix-vector multiplication

In this paper, we consider the implementation of a product c=A b, where A is N1×N3 band matrix with bandwidth ω and b is a vector of size N 3×1, on bidirectional and unidirectional linear systolic arrays (BLSA and ULSA, respectively). We distinguish the cases when the matrix bandwidth ω is 1≤ω≤N 3 and N3≤ω≤N 1+N3-1. A modification of the systolic array synthesis procedure based on data dependencies and space-time transformations of data dependency graph is proposed. The modification enables obtaining both BLSA and ULSA with an optimal number of processing elements (PEs) regardless of the matrix bandwidth. The execution time of the synthesized arrays has been minimized. We derive explicit formulas for the synthesis of these arrays. The performances of the designed arrays are discussed and compared to the performances of the arrays obtained by the standard design procedure.

Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform

In this paper a regular bidirectional linear systolic array (RBLSA) for computing all-pairs shortest paths of a given directed graph is designed. The obtained array is optimal with respect to a number of processing elements (PE) for a given problem size. The execution time of the array has been minimized. To obtain RBLSA with optimal number of PEs, the accommodation of the inner computation space of the systolic algorithm to the projection direction vector is performed. Finally, FPGA-based reprogrammable systems are revolutionizing certain types of computation and digital logic, since as logic emulation systems they offer some orders of magnitude speedup over software simulation; herein, a FPGA realization of the RBLSA is investigated and the performance evaluation results are discussed.

Synthesis of a unidirectional systolic array for matrix–vector multiplication

In this paper we present a procedure, based on data dependencies and space–time transformations of index space, to design a unidirectional linear systolic array (ULSA) for computing a matrix–vector product. The obtained array is optimal with respect to the number of processing elements (PEs) for a given problem size. The execution time of the array is the minimal possible for that number of PEs. To achieve this, we first derive an appropriate systolic algorithm for ULSA synthesis. In order to design a ULSA with the optimal number of PEs we then perform an accommodation of the index space to the projection direction vector. The performance of the synthesized array is discussed and compared with the bidirectional linear SA. Finally, we demonstrate how this array can be used to compute the correlation of two given sequences.

Mapping matrix multiplication algorithm onto fault-tolerant systolic array

An approach to design fault-tolerant hexagonal systolic array (SA) for multiplication of rectangular matrices is described. The approach comprises three steps. First, redundancies are introduced at the computational level by deriving three equivalent algorithms but with disjoint index spaces. Second, we perform the accommodation of index spaces to the projection direction to obtain hexagonal SA with optimal number of processing elements (PE) for a given problem size. Finally, we perform mapping of the accommodated index spaces into fault-tolerant systolic array using valid transformation matrix. As a result, we obtain SA with optimal number of PEs which performs fault-tolerant matrix multiplication. In the case of square matrices of order N × N, this array comprises N 2 + 2N PEs with active computation time t c = 5N − 4 time units. Fault tolerance is achieved through triplicated computation of the same problem instance and majority voting. We have proposed two hardware solutions for the voting process: one when voting is performed at the end of the computation, i.e., at the output of the SA, and the other where voting is performed after each computational step. With the proposed method, any single transient or permanent fault can be detected and corrected. Experimental results show that with the proposed schemes a lot of multiple error patterns can be tolerated, also.

Effect of Neural Network Topology on Flexible Pavement Cracking Prediction

Pavement surface cracking has long been considered an important criterion for maintenance intervention because of its detrimental effects on pavement performance. Once initiated, cracking increases in severity and extent and allows water to penetrate the pavement. The water weakens the unbound layers and consequently accelerates the rate of pavement deterioration. Cracking prediction and its control are thus key components in determining the timing and cost of pavement maintenance. A neural network–based model is presented in this paper for predicting flexible pavement cracking. One‐, two‐, and three‐hidden‐layer backpropagation neural network (BPNN) topologies are investigated and their cracking‐prediction performances compared. Based on the analysis, it is concluded that for the same optimal number of processing elements, a one‐hidden‐layer BPNN topology may be sufficient in achieving satisfactory results in cracking prediction; increasing the number of layers may not add any significant benefit to the performance of the model.

The design of optimal planar systolic arrays for matrix multiplication

The objective of this paper is to provide a systematic methodology for the design of space-time optimal pure planar systolic arrays for matrix multiplication. The procedure is based on data dependence approach. By the described procedure, we obtain ten different systolic arrays denoted as S 1 to S 10 classified into three classes according to interconnection patterns between the processing elements. Common properties of all systolic array designs are: each systolic array consists of n 2 processing elements, near-neighbour communications, and active execution time of 3 n − 2 time units. Compared to designs found in the literature, our procedure always leads to systolic arrays with optimal number of processing elements. The improvement in space domain is not achieved at the cost of execution time or PEs complexity. We present mathematically rigorous procedure which gives the exact ordering of input matrix elements at the beginning of the computation. Examples illustrating the methodology are shown.

Design of space-optimal regular arrays for algorithms with linear schedules

The problem of designing space-optimal 2D regular arrays for N/spl times/N/spl times/N cubical mesh algorithms with linear schedule ai+bj+ck, 1/spl les/a/spl les/b/spl les/c, and N=nc, is studied. Three novel nonlinear processor allocation methods, each of which works by combining a partitioning technique (gcd-partition) with different nonlinear processor allocation procedures (traces), are proposed to handle different cases. In cases where a+b/spl les/c, which are dealt with by the first processor allocation method, space-optimal designs can always he obtained in which the number of processing elements is equal to N/sup 2c. For other cases where a+b>c and either a=b and b=c, two other optimal processor allocation methods are proposed. Besides, the closed form expressions for the optimal number of processing elements are derived for these cases. >

Modular Matrix Multiplication on a Linear Array

A matrix multiplication algorithm on a linear array of processing elements is described. The local storage required by the processing elements and the I/O bandwidth required to drive the array are both constants that are independent of the sizes of the matrices being multiplied. The algorithm is therefore modular, that is, arbitrarily large matrices can be multiplied on a large array built by cascading smaller arrays. Each of the matrix elements is read only once from a fixed I/O port and the algorithm does not use global broadcasting. It is also shown that the proposed algorithm computes the n3 scalar products (where n is the size of the two matrices being multiplied) using an optimal number of processing elements.

Modular matrix multiplication on a linear array

A matrix-multiplication algorithm on a linear array using an optimal number of processing elements is proposed. The local storage required by the processing elements and the I/O bandwidth required to drive the array are both constants that are independent of the sizes of the matrices being multiplied. The algorithm is therefore modular, that is, arbitrarily large matrices can be multiplied on a large array built by cascading small arrays. The array is well-suited for VLSI implementation.