Optical Cache Research Articles

The implementation of dual-band electromagnetically induced transparency metastructure based on micro-strip line structure and Calcium-magnesium-titanium ceramic

In this paper, a metastructure based on micro-strip lines (MSL) structure and Calcium-magnesium-titanium (CMT) is proposed to realize the electromagnetically induced transparency (EIT) phenomenon. In this structure, the MSL as the main structure acts as the bright mode, while the ceramic structure composed of CMT material cylinders acts as the dark mode. The EIT characteristics are simulated and analyzed, while the equivalent circuit model is established. What's more, the EIT effect of the designed structure is verified by experiments, providing convincing evidence for the dual-band EIT performance of the structure. The results show that the dual-band EIT effect is achieved in 0.2 GHz∼1.6 GHz by coupling the CMT structure with the MSL structure, and the values of both transmission peaks reach more than 90%. The physical mechanism of the EIT phenomenon is analyzed by simulating the response of bright mode and dark mode to electromagnetic waves, respectively. Compared with the previously studied EIT MSs, the proposed structure can achieve the EIT effect in dual bands with wider bandwidth, which has a certain application value in the field of optical cache.

Caching With Light: A 16-bit Capacity Optical Cache Memory Prototype

The need of faster access-times and increased memory bandwidths has triggered a concerted research effort towards deploying optical memory circuitry, targeting at the apex of the memory hierarchy pyramid that is traditionally reserved for the fastest access time memory configurations. The advances in integrated photonics allowed for remarkable progress in the field of optical memory implementations, but the majority of optical random-access memory (RAM) demonstrations still expands along single cell developments. A complete optical cache memory demonstration is currently completely missing, with the limited amount of multi-bit optical memory layouts reported so far failing to incorporate the rich organizational and functional framework offered by a cache memory. In this article, we demonstrate experimentally the first 16-bit photonic cache memory hardware prototype, organized in four addressable cache lines with a 4-bit wavelength-division multiplexing (WDM)-optical Data Word stored per line, capable of performing at a 20 Gb/s memory-throughput. The proposed optical cache layout combines a WDM-enabled optical RAM bank and a complete set of cache peripherals, implementing for the first time all cache functionalities directly in the optical domain.

A Practical Shared Optical Cache With Hybrid MWSR/R-SWMR NoC for Multicore Processors

Conventional electronic memory hierarchies are intrinsically limited in their ability to overcome the memory wall due to scaling constraints. Optical caches and interconnects can mitigate these constraints, and enable processors to reach performance and energy efficiency unattainable by purely electronic means. However, the promised benefits cannot be realized through a simple replacement process; to reach its full potential, the architecture needs to be holistically redesigned. This article proposes Pho$, an opto-electronic memory hierarchy architecture for multicores. Pho$ replaces conventional core-private electronic caches with a large shared optical L1 built with optical SRAMs. The shared optical cache is supported by Pho$Net, a novel hybrid MWSR/R-SWMR optical NoC that provides low-latency and high-bandwidth communication between the electronic cores and the shared optical L1 at low optical loss. Pho$Net’s unique network arbitration protocol seamlessly co-arbitrates the request and reply sub-networks and facilitates cache requests and replies that optimize for the common case of cache hits. Through Pho$ we solve the problems that render previous designs impractical. Our results show that Pho$ achieves on average 1.41× performance speedup (3.89× max) and 31% lower energy-delay product (90% max) against conventional designs. Moreover, the Pho$Net optical NoC for core-cache communication consumes 70% less power compared to directly applying previously proposed optical NoC architectures.

Optics in Computing: From Photonic Network-on-Chip to Chip-to-Chip Interconnects and Disintegrated Architectures

Following a decade of radical advances in the areas of integrated photonics and computing architectures, we discuss the use of optics in the current computing landscape attempting to redefine and refine their role based on the progress in both research fields. We present the current set of critical challenges faced by the computing industry and provide a thorough review of photonic Network-on-Chip (pNoC) architectures and experimental demonstrations, concluding to the main obstacles that still impede the materialization of these concepts. We propose the employment of optics in chip-to-chip (C2C) computing architectures rather than on-chip layouts toward reaping their benefits while avoiding technology limitations on the way to manycore set-ups. We identify multisocket boards as the most prominent application area and present recent advances in optically enabled multisocket boards, revealing successful 40 Gb/s transceiver and routing capabilities via integrated photonics. These results indicate the potential to bring energy consumption down by more than 60% compared to current QuickPath Interconnect (QPI) protocol, while turning multisocket architectures into a single-hop low-latency setup for even more than four interconnected sockets, which form currently the electronic baseline. We go one step further and demonstrate how optically-enabled eight-socket boards can be combined via a 256 × 256 Hipoλaos Optical Packet Switch into a powerful 256-node disaggregated system with less than 335 ns latency, forming a highly promising solution for the latency-critical rack-scale memory disaggregation era. Finally, we discuss the perspective for disintegrated computing via optical technologies as a mean to increase the number of synergized high-performance cores overcoming die area constraints, introducing also the concept of cache disintegration via the use of future off-die ultrafast optical cache memory chiplets.

An optically-enabled chip–multiprocessor architecture using a single-level shared optical cache memory

We present an optical bus-based chip–multiprocessor architecture where the processing cores share an optical single-level cache implemented in a separate chip next to the Central-Processing-Unit (CPU) die. The interconnection system is realized through Wavelength-Division-Multiplexed optical interfaces connecting the shared cache with the cores and the Main-Memory via spatial-multiplexed waveguides. Evaluating the proposed approach, we realize system-level simulations of a wide-range parallel workloads using Gem5. Optical cache architecture is compared against the conventional one that uses dedicated on-chip Level-1 electronic caches and a shared Level-2 cache. Results show significant Level-1 miss rate reduction of up to 96% for certain cases; on average, a performance speed-up of 19.4% or cache capacity requirements reduction of ~63% is attained. Combined with high-bandwidth CPU-Dynamic Random Access Memory (DRAM) bus solutions based on optical interconnects, the proposed design is a promising architecture bridging the gap between high-speed optically connected CPU-DRAM schemes and high-speed optical memory technologies.

All-Optical Tag Comparison for Hit/Miss Decision in Optical Cache Memories

An all optical multi-wavelength tag comparator unit followed by a semiconductor optical amplifier-read access gate (SOA-RAG) is presented for all-optical cache memory architectures. Proof-of-principle operation of the Tag Comparison (TC) circuit as a dual-bit tag-comparison stage is presented by exploiting cross-phase modulation-based XOR logic gates based on SOA-Mach–Zehnder interferometers (SOA-MZIs), in order to decide upon a cache hit or cache miss operation, while the two SOA-MZI outputs control the ON/OFF cross-gain-modulation of the SOA-RAG unit. Experimental error free operation is demonstrated for a $8\,\times \,10$ -Gb/s wavelength division multiplexing (WDM) formatted optical word signal and a $4\times 10$ -Gb/s WDM tag.

Optical Buffering for Chip Multiprocessors: A 16GHz Optical Cache Memory Architecture

We demonstrate a 16GHz physical layer optical cache memory architecture for direct mapping associativity, organized in four cache lines with every line being capable of storing two bytes of optical data. WDM formatting of both the memory address and the optical data words is exploited, while the proposed design relies on the interconnection of subsystems that comprise experimentally proven optical building blocks. The performance of the optical cache is evaluated via physical layer simulations showing successful functionality both during Read and Write operation. Going a step further and considering a higher capacity optical cache module, we present its impact when performing with true processor workload benchmarks in Chip Multiprocessor configurations, employed as a L1 cache shared among multiple cores. Its performance is compared with the conventional electronic CMP topology, where dedicated L1 electronic caches and a shared L2 cache are used, showing that the use of optical 16GHz cache can lead to performance speed-up up to 40% while reducing the cache total capacity requirements by 84%. With optical interconnects having already resulted to high-bandwidth CPU-memory bus solutions, our optical cache architecture forms a fully compatible system solution for bridging the gap between optically connected CPU-cache schemes and high-speed optical RAM cell solutions.

Optical Cache Memory Peripheral Circuitry: Row and Column Address Selectors for Optical Static RAM Banks

We demonstrate WDM-enabled all-passive optical row and column address selector (RAS/CAS) circuits for use as optical static RAM (SRAM) bank peripherals in future optical cache memory implementations. We show that the introduction of the wavelength dimension in both the memory address and data word fields can lead to RAS and CAS architectures that rely exclusively on all-passive wavelength-selective configurations. An all-optical 2 × 4 RAS comprising a wavelength-selective filtering matrix (λ-matrix) and a wavelength-based CAS unit formed by a simple AWG element are demonstrated in proof-of-principle experiments at 10 Gb/s with error-free operation at 10 -9 BER value using two different types of WDM SRAM row Access Gate (AG): a cross-phase modulation SOA-MZI gate and a single SOA cross-gain modulation gate, with the first providing the higher performance compared to SOA module and the second offering lower power requirements between the two WDM AG. A chip-scale optical cache peripheral circuitry development path using Silicon-on-Insulator (SOI) ring resonators for the λ-matrix implementation is also presented and the proposed architecture is evaluated via physical layer simulations using SOAs as SRAM row AGs at 10 Gb/s for a 16×4 optical SRAM bank. Moreover, we discuss on possible improvements towards reducing insertion losses of the RAS/CAS modules in order to allow for increased block sizes. Finally, we provide a detailed analysis on the design and parameter specifications required for RAS and CAS block size scaling towards supporting higher-capacity optical SRAM banks.

Bringing WDM Into Optical Static RAM Architectures

Optical RAM appears to be the alternative approach towards overcoming the “Memory Wall” of electronics, suggesting use of light in RAM architectures to enable ps-regime memory access times. In this communication we take advantage of the wavelength properties of optical signals to present new architectural perspectives in optical RAM structures by introducing the WDM principles in the storage area. To this end, we report on a 4 × 4 WDM optical RAM bank architecture that exploits a novel SOA-based multi-wavelength Access Gate (WDM-AG) and a dual wavelength SOA-based SET-RESET All-Optical Flip Flop (AOFF) as fundamental building blocks. The WDM-AG enables simultaneous random access to a 4-bit optical word encoded in 8 different wavelengths, allowing for the four AOFFs of each RAM row to effectively share the same Access Gate. The scheme is shown to support a 10 Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15 mW/Gbit/s for the WDM-AG and 120 mW/Gbit/s for the AOFFs. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption, while enabling for re-configurability in optical cache mapping.

Read times for bacteriorhodopsin-film optical cache memory

We report measurements of nonlinear-optical responses of bacteriorhodopsin (BR) films of long intermediate-state lifetimes. Nanosecond-duration pulses were used as the excite beam and cw monochromatic light was used as the probe beam in excite–probe experiments. The results reveal that, whereas the response time of the BR films is of the order of milliseconds at the probe wavelength of 633 nm used in earlier experiments, it is of the order of 100 µs at probe wavelengths of 600 nm and below. Contrast ratios and insertion losses were also measured at different probe wavelengths and probe irradiance levels; the maximum contrast ratio was found to be ∼3:1. The implications of these results for the application of BR films as optical cache memory devices are discussed.

Characterisation of Long M-State Lifetime Bacteriorhodopsin Thin Films for Optical Cache Memory

We report the optical characterisation of bacteriorhodopsin (BR) films of long intermediate-state lifetimes. The M-state lifetime is extended from 10 ms for the native BR protein to ∼20 minutes for our BR films, by chemical and physical modifications of the material. Optical cache memory characteristics of thin films are studied in excite-probe experiments in which nanosecond-duration pulses are used to excite a BR film and cw monochromatic light used to monitor the transmission dynamics. The memory read-time is found to vary significantly with the probe wavelength; it is of the order of milliseconds at 633 nm and of the order of 100 µs for probe wavelengths of 600 nm and below. The memory erase-time is ∼50 µs. Contrast ratios and insertion losses are measured at different probe wavelengths, with a maximum contrast ratio following nanosecond excitation of ∼3:1 obtained in the peak absorption region of the B-state ( ∼570 nm), at an excitation fluence of 30 mJcm-2. The implications of these results for the application of BR films as optical cache memory devices are discussed.

Nanosecond optical excitation dynamics of long M-state lifetime bacteriorhodopsin films

Dynamic parameters relevant to the performance of bacteriorhodopsin (bR) as an optical cache memory are reported. The thermal relaxation of the M-state photocycle-intermediate has been a barrier to the exploitation of wild-type bR in optical memory devices. Extension of the room-temperature M-state lifetime from 10 ms to ∼10 s is described. Writing to the long-lifetime material is achieved for nanosecond pulses of less than 1 nJ μm −2 fluence. Reading, at a contrast-ratio of 1.3:1, is achievable following a 5 ms delay. Erasure is achieved on a 50 μs timescale for pulse fluences similar to those used for the writing stage. Following continuous-wave (cw) excitation, contrast ratios of 200:1 are obtained, with significant photochromic changes remaining after many seconds.