Operational Transconductance Amplifier Research Articles

Compact grounded memristor model with resistorless and tunability features

This research article provides a circuit illustration of a grounded memristor emulator. An operational transconductance amplifier (OTA) is one of its active components, along with two transistors and one capacitor. With a simple flip of the input ports, the incremental and decremental settings for the proposed memristor may be preserved. With the capacity to function in the megahertz band, the circuit offers a resistorless and controllable feature. Using the Cadence Virtuoso EDA tool in an analog design environment (ADE), PSPICE simulation with 0.18 µm TSMC technology parameter has been used to illustrate the viability of the suggested memristor. It has been confirmed in the simulation section that the operating frequency and tunability responses in the current-voltage (I-V) plane are in reasonable agreement with the theory. The suggested memristor model’s resilience has also been tested using process corner, Monte Carlo analysis, and temperature analyses, as well as single and parallel connected structures. The suggested memristor model is simple and does not need additional sub-circuit components, making it appropriate for implementation in integrated circuits. The experimental demonstration has been carried out by making a prototype on a breadboard using ICs, which exhibits good agreement with theoretical and simulation results. Single/parallel combinations of memristor, chaotic oscillator, and high pass filter have been presented to demonstrate its application.

Research on Techniques for Enhancing the Speed of Low-Power Operational Amplifier

In the context of low utilization, this paper explores various techniques for enhancing the speed of operational amplifier (OA). The main text delves into three methods to gain equilibrium: fully differential operational amplifier (FDA), twostage operational transconductance amplifier (OTA), and a novel high-speed calculation system architecture employing a “rhombus crystal tube.” The FDA improves speed by minimizing noise and enhancing bandwidth and output voltage swing, without increasing power consumption. The design of the two-stage OTA combines the characteristics of a differential amplifier and a telescopic amplifier, optimizing gain and slew rate through Miller compensation and noise gain manipulation, thereby achieving high-speed performance. A novel high-speed operational amplifier structure employs diamond transistors to supply substantial current for capacitor charging, enhancing the slew rate and overall speed. Throughout the text, these methods are presented as a means to jointly promote high speed, low power consumption, and the handling of a significant number of transistors. To further increase the speed, the size of the microcrystalline tube is crucial. The research direction is outlined, and while the design equipment is in the foreground, there remains room for progress, especially in applications for large-scale electrical models. Future research aims to enhance the power efficiency of circuits, making them more practical and efficient. This study provides valuable insights into balancing power consumption and speed in advanced electronic devices.

Graphene nanoribbon FET technology‐based OTA for optimizing fast and energy‐efficient electronics for IoT application: Next‐generation circuit design

AbstractThe Internet of Things (IoT) and portable electronic devices are pivotal in enhancing living standards, with battery efficiency and compact design being critical for these devices. Analogue sensors, integral to advanced artificial intelligence, often necessitate complex real‐time processing and actuation. This study examines the performance of one‐dimensional armchair graphene nanoribbons in graphene nanoribbon field‐effect transistors (GNRFETs). It compares graphene nanoribbon‐based triple cascode operational transconductance amplifiers (GNRFET‐TCOTAs) with conventional CMOS‐based TCOTA. The results reveal substantial enhancements in the GNRFET‐based TCOTAs: the pure GNR‐TCOTA variant shows a remarkable 33.8% increase in DC gain and significant improvements in transconductance, slew rate, and gain‐bandwidth, with enhancements of 8.48, 5.85, and 8.56 times, respectively. Furthermore, the pure GNRFET TCOTA exhibits higher speed, lower energy‐delay product, and settling time compared to Si‐CMOS‐based TCOTA. The study also investigates the impact of critical design parameters on circuit performance. Overall, the research highlights the potential of GNRFETs to optimize TCOTA circuits, offering a path towards more efficient and compact electronic devices, thereby advancing the state of nanoelectronics and supporting the growth of high‐performance IoT systems.

Open and Collaborative Dataset for the Classification of Operational Transconductance Amplifiers for Switched-Capacitor Applications

Open and Collaborative Dataset for the Classification of Operational Transconductance Amplifiers for Switched-Capacitor Applications

16-nW 0.5-V low-pass filter for bio-signal applications

A low-voltage, ultra-low power fully differential low-pass filter for bio-signal applications using multiple-input fully differential operational transconductance amplifiers (OTA) is presented in this article. The multiple inputs of OTA can be achieved using multiple-input dynamic threshold MOS transistor (MIDT-MOST) technique. The novelty of this work is to exhibit the proposed filter using multiple-input OTAs, which leads to a reduction in the number of active OTAs and power consumption. The fourth-order low-pass filter that is cascaded by two second-order filters has been presented. The fourth-order low-pass filter is designed and simulated in the Cadence environment using the 0.18 μm CMOS technology from TSMC at a supply voltage of 0.5 V. The simulation results show that the filter consumes 16 nW of power at a bandwidth of 110 Hz, has a total harmonic distortion (THD) of 1 % at 204.96 mV input amplitude, and provides dynamic range of 69.24 dB. These results indicate that the proposed low-pass filter can be applied to bio-signal processing applications.

High‐speed, two‐stage operational transconductance amplifier without Miller capacitor, suitable for large capacitive load

AbstractA two‐stage Class A‐AB operational transconductance amplifier with low power consumption, high slew rate, and high bandwidth is introduced for handling large capacitive loads. Unlike the conventional two‐stage operational transconductance amplifiers that use a Miller capacitor, compensation is provided by the load capacitor (CL) at the output node. The proposed two‐stage amplifier maintains a 45° phase margin (PM) over any load capacitance. This is achieved through a MOSFET‐based RC network at the output node. Dual nMOS/pMOS differential stages drive output directly, improving both SR+ and SR−. Post‐layout simulation results with a capacitive load of 100 pF (CL) demonstrate that the proposed operational transconductance amplifier has a DC gain of 60.1 dB, an excellent average slew rate of 20.3 V/µs, a gain‐bandwidth product of 10.6 MHz, an average 1% settling time of 122.2 ns and a PM of 76.6°, while consuming only 103.5 µW. Reducing the CL to 10 pF reduces the PM to 47.6°, while increasing the gain‐bandwidth and average slew rate to 82.9 MHz and 142.6 V/µs respectively.

Design of an operational transconductance amplifier configuration using machine learning

Design of an operational transconductance amplifier configuration using machine learning

A local positive feedback loop-reused technique for enhancing performance of folded cascode amplifier

A current-reused folded cascode operational transconductance amplifier (OTA) using a local positive feedback (LPFB) technique has been proposed in previous literature, which does not achieve maximum unity gain-bandwidth (GBW). Besides, the stability of LPFB in the LPFB-OTA is limited by local common mode feedback (LCMFB) resistors. Based on the analysis, a local positive feedback loop-reused (LPFBR) technique is proposed to improve the performance of conventional LPFB OTA. For a fair comparison, both conventional and proposed OTAs working at saturation region are designed and simulated in SMIC 0.18μm process. The simulated results demonstrate that the proposed LPFBR-OTA has almost 10.5 times the bandwidth and maintains stability compared to that of the conventional LPFB-OTA under the condition that LCMFB resistors are increased by a factor of 10.

A three-stage single-miller CMOS OTA with no lower load capacitor limit

This work proposes a Single Miller Capacitor (SMC) compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors with a zero minimum load capacitor. The proposed three-stage OTA does not require a minimum load capacitor for OTA to be stable. The proposed work uses two different feed-forward transconductors to enhance the small-signal and large-signal performances of the OTA. This OTA achieves more than 70° phase margin and more than 10dB gain margin with a load capacitor range of 0 to 500pF and consumes less quiescent current. The proposed OTA uses a smaller SMC of 2pF to drive a wide range of load capacitors. Furthermore, it saves the active area of the chip. The proposed OTA is simulated in a cadence virtuoso tool using UMC 90nm CMOS technology with BSIM4 MOSFETs.

An Ultra-Low-Voltage Transconductance Stable and Enhanced OTA for ECG Signal Processing.

In this paper, a rail-to-rail transconductance stable and enhanced ultra-low-voltage operational transconductance amplifier (OTA) is proposed for electrocardiogram (ECG) signal processing. The variation regularity of the bulk transconductance of pMOS and nMOS transistors and the cancellation mechanism of two types of transconductance variations are revealed. On this basis, a transconductance stabilization and enhancement technique is proposed. By using the "current-reused and transconductance-boosted complementary bulk-driven pseudo-differential pairs" structure, the bulk-driven pseudo-differential pair during the input common-mode range (ICMR) is stabilized and enhanced. The proposed OTA based on this technology is simulated using the TSMC 0.18 μm process in a Cadence environment. The proposed OTA consumes a power below 30 nW at a 0.4 V voltage supply with a DC gain of 54.9 dB and a gain-bandwidth product (GBW) of 14.4 kHz under a 15 pF capacitance load. The OTA has a high small signal figure-of-merit (FoM) of 7410 and excellent common-mode voltage (VCM) stability, with a transconductance variation of about 1.35%. Based on a current-scaling version of the proposed OTA, an OTA-C low-pass filter (LPF) for ECG signal processing with VCM stability is built and simulated. With a -3 dB bandwidth of 250 Hz and a power consumption of 20.23 nW, the filter achieves a FoM of 3.41 × 10-13, demonstrating good performance.

A novel tunable capacitively-copuled instrumentation amplifier with 14.4 nV/ [formula omitted] z) noise and 190.47 nW micro-power for ECG applications

This paper describes a low-power, low-noise capacitively-coupled instrumentation amplifier (CCIA) designed for capturing biopotential signals. The main advantage of proposed design are as (i) CCIA based on new IA has been proposed, (ii) the lower cutoff frequency has been improved by adding MOS based resistor, (iii) gm enhancement circuit is added in operational transconductance amplifier (OTA) based fully differential difference amplifier (FDDA)to improve gain and bandwidth. The DC electrode-offset voltage is reduced and the input impedance is increased by using feedback mechanism. Cadence EDA tool is used to analyze the findings of the proposed CCIA's in 0.18 μm, CMOS technology with a 1.8 V power supply. The proposed CCIA architecture has an adjustable mid-band gain from 52.55 to 61.11 dB for bias voltage ranges from 0.1 to 0.6 V, frequency range of 0.06 Hz–1.72 kHz, and a CMRR of 122 dB. The proposed CCIA has a total power dissipation of 190.47 nW and equivalent input referred noise (IRN) of 14.4 nV/sqrtHz at 0.01 Hz. It only occupies 0.01 mm2 of core area. To assess the robustness of suggested design, PVT analysis, post layout simulation and a comparison with previously published works demonstrates the competence of the design.

A High Gain, Low Power Operational Transconductance Amplifier Capable of Recording and Processing ECG Signals

Based on high output resistor current mirrors and differential pair inputs, a new operational transconductance amplifier (OTA) is designed in this paper that can collect, filter, denoise and amplify electrocardiogram (ECG) signals. The OTA is designed on a 0.18μm CMOS process with a supply voltage of 1.8V. In this experiment, the ECG signal generated by the human model is first simulated, which has a noise of 50 Hz from electromagnetic interference, especially the electrical power lines. The differential input pair is then connected to the model, and it is proved that it can denoise the common-mode noise. Finally, the designed OTA is connected to the manikin, and the experimental results are compared with the traditional OTA. The design achieves a differential-mode gain of 43.56dB and a common-mode gain of -31.36dB while maintaining a differential input voltage swing of 1Vpp. Experimental results show that the OTA can denoise and amplify the ECG signal without distortion.

A 0.5 V, 32 nW Compact Inverter-Based All-Filtering Response Modes Gm-C Filter for Bio-Signal Processing

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter’s frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing.

Analysis of an operational trans-conductance amplifier with positive feedback

In this paper, we present an analysis of an operational trans-conductance amplifier (OTA) with two positive feedback. The direct current (DC) transfer function is obtained by analyzing the OTA using the drain current in the weak inversion region. The analysis results were verified through comparison with SPICE simulations, and the characteristics of the DC transfer function analysis for the OTA design are well matched with the simulation results. The designed OTA dissipates a low power of 41.4 nW, and features the slew rate is improved by 436% compared to a conventional OTA without two positive feedback. Additionally, a DC gain and a unity-gain bandwidth is improved by 36 dB and 6.7 times, respectively. The OTAs are designed for the 0.18 μm complementary metal–oxide–semiconductor (CMOS) process.

Ultra-low-power super class-AB adaptive biasing operational transconductance amplifier with enhanced gain for biomedical applications

The operational transconductance amplifier (OTA) proposed in this article is a bulk-driven (BD), single-stage, super-class-AB, adaptive biasing, functioning in the subthreshold region (ST) with an enormously low power supply of ± 0.25 V, providing high-gain. The input core of the OTA circuit is composed of adaptively biased BD differential input pairs based on flipped voltage follower (FVF), which drive in class-AB mode with a partial positive feedback (PPF) approach. The circuit additionally employs FVF and self-cascode (SC)-based low-power current mirror loads at its output to obtain significantly high gain and unity gain frequency. In addition, using adaptive loads based on source-degenerated metal oxide semiconductor (MOS) resistors raises dynamic current more efficiently, consequently improving the slew rate and unity gain frequency (UGF) without drawing additional power. Employing the cadence spectre tool and the UMC 0.18 μm complementary metal oxide semiconductor (CMOS) process technology, the designed OTA has been simulated. The simulation outcomes substantiate that the amplifier provides high open loop DC gain of 75 dB, 18.75 kHz UGF with a phase margin of 63.93º, and input-referred noise (IRN) of 0.734 µV/Hz0.5 at 1 kHz frequency. The proposed OTA consumes just 60.15 nW of power. The performance results confirmed that the proposed OTA circuit is appropriate in biomedical applications.

A low-voltage, high-performing CMOS transistor based on multiple- output operation transconductance amplifier for current mode KHN Universal filter applications

This study proposes a current-mode KHN universal filter design that can perform three standard functions simultaneously: low-pass, high-pass, and band-pass. The circuit is built around a multiple-output operation transconductance amplifier (MO-OTA), which allows for electronically adjustable pole frequency and quality factor by modifying input bias currents (IB). The circuit layout is straightforward, with two MO-OTAs and two grounded capacitors, eliminating the need for external resistors and depending entirely on grounded components. Because of its simplicity, the circuit is suited for use in a tiny, efficient design. The proposed circuit's operation was validated using LT-Spice simulations, and the results were in line with theoretical expectations. The circuit used around 298μW of power at ±0.2V power supply voltages. These results demonstrate the circuit's potential for low-power applications, which are crucial in many modern electronic devices. The suggested current-mode KHN universal filter offers a viable option for combining various filter functions in a single circuit with customizable parameters. Its simplicity, efficiency, and performance qualities make it a feasible choice for incorporation into a variety of electronic systems, allowing for more filter design freedom.

An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA.

Design and Characterization of a Digitally Tunable Gm-C Filter for Multi-Standard Receivers

This paper presents the design, simulation, prototyping, and measurement results of a digitally tunable fourth order Gm-C low-pass filter (LPF) for multi-standard radio receivers. The LPF cut-off frequency can be tunned by digitally selecting the transconductance of the basic reconfigurable operational transconductance amplifiers (OTAs) that compose the circuit. Four operation modes allow for control of the OTA transconductances and, consequently, the scaling of power consumption. The filter was designed and prototyped in a 1.8 V 180 nm CMOS process. The measurement results indicate that the configurability provides a cutoff frequency of 1.90/3.56/6.07/8.15 MHz with a power consumption ranging from 9.9 to 13.1 mW. The designed filter achieves an IIP3 of 8.17 dBm for a signal bandwidth of 8.15 MHz. The performance, in terms of power dissipation, noise, and cut-off frequency, is at the same order of magnitude compared to recent related works reported in the literature. The advantages are a compact area, small sensitivity to component mismatches, and low design complexity. The proposed filter presents electrical characteristics suitable for the application in radio receivers for multi-carrier WCDMA signals.

A novel resistorless memristor emulator circuit and its implementation of chaotic Jerk system

This work presents a novel resistorless memristor emulator circuit designed in both grounded and floating configurations. The grounded memristor consists of a Current-Controlled Current Conveyor Transconductance Amplifier (CC-CCTA) and a capacitor. On the other hand, a floating memristor includes a CC-CCTA and a capacitor, along with an additional Operational Transconductance Amplifier (OTA). These proposed emulators are electronically controllable owing to the internal structures of active elements. Theoretical analysis and simulation results have been obtained for the proposed designs. Simulation results have been conducted utilizing the LTspice program and TSMC 180 nm technology has been used for internal structures. In these results, the effects of the changing capacitor values, different frequencies, electronic tunability, reactions to temperature change, and pulse response have been investigated. Subsequently, a chaotic Jerk circuit has been implemented incorporating the proposed memristor emulator. The chaotic behavior of the floating memristor has been investigated using the LTspice simulation software.

Low‐power multibit delta–sigma modulator based on passive and unattenuated summation scheme

AbstractA low‐power multibit delta–sigma modulator (DSM) based on a passive and unattenuated summation scheme is proposed. The summation circuit achieves multiplication of the voltage signal carried on the summation capacitor through a bidirectional sampling technique, thereby compensating for the inherent attenuation caused by passive summation, which eliminates the need for an active operational transconductance amplifier (OTA) to achieve perfect summation. Here, a second‐order DSM based on a 4‐bit first‐order passive noise‐shaping (NS) SAR quantizer is employed to satisfy the SNDR requirements exceeding 100 dB, which validates the reliability of the summation scheme. In addition, a cascoded floating inverter amplifier (FIA) is used as the core OTA to further improve system energy efficiency. Simulation results demonstrate that at a supply voltage of 1.2 V and a bandwidth of 20 kHz, the SNDR reaches 102.62 dB, power consumption is only 148.32 μW, and the Schreier figure‐of‐merit (FoM) of the SNDR is 183.92 dB. The results demonstrate that the proposed DSM has considerable potential for widespread application in the audio domain.