Virtual Memory Operating System Research Articles

In lieu of swap: Analyzing compressed RAM in Mac OS X and Linux

The forensics community is increasingly embracing the use of memory analysis to enhance traditional storage-based forensics techniques, because memory analysis yields a wealth of information not available on non-volatile storage. Memory analysis involves capture of a system's physical memory so that the live state of a system can be investigated, including executing and terminated processes, application data, network connections, and more. One aspect of memory analysis that remains elusive is investigation of the system's swap file, which is a backing store for the operating system's virtual memory system. Swap files are a potentially interesting source of forensic evidence, but traditionally, most swap file analysis has consisted of string searches and scans for small binary structures, which may in some cases be revelatory, but are also fraught with provenance issues. Unfortunately, more sophisticated swap file analysis is complicated by the difficulty of capturing mutually consistent memory dumps and swap files, the increasing use of swap file encryption, and other issues. Fortunately, compressed RAM facilities, such as those in Mac OS X Mavericks and recent versions of the Linux kernel, attempt to reduce or eliminate swapping to disk through compression. The storage of compressed pages in RAM both increases performance and offers an opportunity to gather digital evidence which in the past would have been swapped out. This paper discusses the difficulty of analyzing swap files in more detail, the compressed RAM facilities in Mac OS X and Linux, and our new tools for analysis of compressed RAM. These tools are integrated into the open-source Volatility framework.

Online memory compression for embedded systems

Memory is a scarce resource during embedded system design. Increasing memory often increases packaging costs, cooling costs, size, and power consumption. This article presents CRAMES, a novel and efficient software-based RAM compression technique for embedded systems. The goal of CRAMES is to dramatically increase effective memory capacity without hardware or application design changes, while maintaining high performance and low energy consumption. To achieve this goal, CRAMES takes advantage of an operating system's virtual memory infrastructure by storing swapped-out pages in compressed format. It dynamically adjusts the size of the compressed RAM area, protecting applications capable of running without it from performance or energy consumption penalties. In addition to compressing working data sets, CRAMES also enables efficient in-RAM filesystem compression, thereby further increasing RAM capacity. CRAMES was implemented as a loadable module for the Linux kernel and evaluated on a battery-powered embedded system. Experimental results indicate that CRAMES is capable of doubling the amount of RAM available to applications running on the original system hardware. Execution time and energy consumption for a broad range of examples are rarely affected. When physical RAM is reduced to 62.5% of its original quantity, CRAMES enables the target embedded system to support the same applications with reasonable performance and energy consumption penalties (on average 9.5% and 10.5%), while without CRAMES those applications either may not execute or suffer from extreme performance degradation or instability. In addition to presenting a novel framework for dynamic data memory compression and in-RAM filesystem compression in embedded systems, this work identifies the software-based compression algorithms that are most appropriate for use in low-power embedded systems.

Compiler-directed page coloring for multiprocessors

This paper presents a new technique, compiler-directed page coloring, that eliminates conflict misses in multiprocessor applications. It enables applications to make better use of the increased aggregate cache size available in a multiprocessor. This technique uses the compiler's knowledge of the access patterns of the parallelized applications to direct the operating system's virtual memory page mapping strategy. We demonstrate that this technique can lead to significant performance improvements over two commonly used page mapping strategies for machines with either direct-mapped or two-way set-associative caches. We also show that it is complementary to latency-hiding techniques such as prefetching.We implemented compiler-directed page coloring in the SUIF parallelizing compiler and on two commercial operating systems. We applied the technique to the SPEC95fp benchmark suite, a representative set of numeric programs. We used the SimOS machine simulator to analyze the applications and isolate their performance bottlenecks. We also validated these results on a real machine, an eight-processor 350MHz Digital AlphaServer. Compiler-directed page coloring leads to significant performance improvements for several applications. Overall, our technique improves the SPEC95fp rating for eight processors by 8% over Digital UNIX's page mapping policy and by 20% over a page coloring, a standard page mapping policy. The SUIF compiler achieves a SPEC95fp ratio of 57.4, the highest ratio to date.

Compiler-directed page coloring for multiprocessors

This paper presents a new technique, compiler-directed page coloring, that eliminates conflict misses in multiprocessor applications. It enables applications to make better use of the increased aggregate cache size available in a multiprocessor. This technique uses the compiler's knowledge of the access patterns of the parallelized applications to direct the operating system's virtual memory page mapping strategy. We demonstrate that this technique can lead to significant performance improvements over two commonly used page mapping strategies for machines with either direct-mapped or two-way set-associative caches. We also show that it is complementary to latency-hiding techniques such as prefetching.We implemented compiler-directed page coloring in the SUIF parallelizing compiler and on two commercial operating systems. We applied the technique to the SPEC95fp benchmark suite, a representative set of numeric programs. We used the SimOS machine simulator to analyze the applications and isolate their performance bottlenecks. We also validated these results on a real machine, an eight-processor 350MHz Digital AlphaServer. Compiler-directed page coloring leads to significant performance improvements for several applications. Overall, our technique improves the SPEC95fp rating for eight processors by 8% over Digital UNIX's page mapping policy and by 20% over a page coloring, a standard page mapping policy. The SUIF compiler achieves a SPEC95fp ratio of 57.4, the highest ratio to date.

Avoiding conflict misses dynamically in large direct-mapped caches

This paper describes a method for improving the performance of a large direct-mapped cache by reducing the number of conflict misses. Our solution consists of two components: an inexpensive hardware device called a Cache Miss Lookaside (CML) buffer that detects conflicts by recording and summarizing a history of cache misses, and a software policy within the operating system's virtual memory system that removes conflicts by dynamically remapping pages whenever large numbers of conflict misses are detected. Using trace-driven simulation of applications and the operating system, we show that a CML buffer enables a large direct-mapped cache to perform nearly as well as a two-way set associative cache of equivalent size and speed, although with lower hardware cost and complexity.

Avoiding conflict misses dynamically in large direct-mapped caches

This paper describes a method for improving the performance of a large direct-mapped cache by reducing the number of conflict misses. Our solution consists of two components: an inexpensive hardware device called a Cache Miss Lookaside (CML) buffer that detects conflicts by recording and summarizing a history of cache misses, and a software policy within the operating system's virtual memory system that removes conflicts by dynamically remapping pages whenever large numbers of conflict misses are detected. Using trace-driven simulation of applications and the operating system, we show that a CML buffer enables a large direct-mapped cache to perform nearly as well as a two-way set associative cache of equivalent size and speed, although with lower hardware cost and complexity.

Extending multiprogramming to a DMPP

Chagori is a multi-user, multi-tasking virtual memory operating system with demand paging. It is designed for the K2 distributed memory parallel processor (DMPP) under development at our laboratory. Chagori is one of the first operating systems for DMPPs that allows multiple users to concurrently run and to interactively debug large parallel programs on a DMPP. This paper concentrates on scheduling and paging issues that arise from extending the principles of multiprogramming to tightly coupled parallel programs running on a machine which provides both coarse and fine grain communication.

A study of program restructuring in a virtual memory system

The effects of module restructuring on the behavior of programs are measured in a multiuser virtual memory operating system. Comparisons are made of the performance improvement as a function of the restructuring technique used. It is found that the improvement depends on the level of memory contention in the system. Measurements show that even the very simplest restructuring techniques can give a significant improvement in program paging behavior, and that these simple techniques may be adequate in many cases. Discussion includes guidelines on the conditions under which program restructuring will be productive.

The New National Control Centre, Ireland

The new National Control Centre for the Electricity Supply Board (ESB), Ireland, currently undergoing site commissioning, will be in operation in September 1986. The Control Centre will control a single 2200 MW island network. The control centre is being supplied under a supply contract with Landis & Gyr, Zug, Switzerland. There is a high degree of customer participation and emphasis is laid on customer interfacing. The central hardware comprises a dual main 32-bit computer system with Virtual Memory Operating System, four dual front-end processors and four display processors. Remote Terminal Units communicate with the Control Centre on a private communication network, mostly Microwave and Power Line Carrier. This paper describes the control centre in a general way with emphasis on contractual arrangements, customer involvement and testing procedures.

Data management in FEM-based optimization software

A programming approach for design of software system for FEM-based optimization techniques is presented. The main emphasis of the paper is on presentation of techniques for efficient data management. General organization pf a design software system, called SADDLE, is given which utilizes the data management system presented. Main features of the SADDLE system are: modularity, efficient data management, software portability and efficiency on virtual and non-virtual machines. Numerical results are presented which show relative efficiency of the SADDLE data manager for a large structural design problem compared to the PRIMOS virtual memory operating system.

The evolution of the operating system EMAS 2900

AbstractAs a result of experiencing problems with manufacturer's software on the early 2900 machines Edinburgh University took the bold step of attempting to move the general purpose timesharing system EMAS from an ICL 4–75 to an ICL 2970 computer. This paper describes the move together with the changes made and includes some preliminary performance figures from the new system. This implementation project has produced a major time‐sharing virtual memory operating system with a fraction of the effort required to implement the original system.

Throughput Capacity of a Sequence of Queues with Blocking Due to Finite Waiting Room

A tandem queueing system with blocking due to finite waiting room is considered. Maximum throughput is studied by an approximation for several cases. The service time can depend on the number of customers; intermediate arrivals can also be allowed. Some special models with two stations in sequence and blocking are examined. These models are used for the performance evaluation of computer systems. In particular, the maximum throughput for a virtual memory operating system and for a node-to-node protocol in a computer network are obtained.

Multiprogramming with virtual memory—a queueing model

A multiprogramming computing system which utilizes a virtual memory operating system, with paging-on-demand, is defined in queueing-theoretic terms. The validity and possible uses of such a model are discussed. Several quantities and measures of effectiveness, such as paging time, total system response time, and memory requirements are computed. The discussion and analysis place emphasis on exact, computable results.

Evaluation of markov program models in virtual memory systems

AbstractA first order Markov model of program behaviour is developed from FORTRAN program instruction data. The program model is evaluated by using it to generate page references for input into a simple virtual memory operating system (VMOS) simulation model. The actual trace data are also used to drive the VMOS model. In both cases the fault probability is obtained for different replacement rules, memory sizes and page sizes. A comparison of fault probabilities is used to determine the effectiveness of the Markov program model.