This paper pontificates on design and realization of low-cost single phase single stage modified interleaved Sepic (MILS) converter for power supplies. On contrary to the classical Sepic power converters, the introduced active power factor correction (APFC) converter involves simple idea of paralleling that enables low input and output ripples with minimal device count. The interleaving conceptualization also lessens current stresses and static losses. Also, this modified power processing converter reveals natural power factor correction (PFC) and zero current switching (ZCS) features by discontinuous conduction mode (DCM) operation. Furthermore, the practical corroboration of the proposed converter is built and tested for 250 W hardware model to affirm benefits with 92 % efficiency and their relevant outcomes are reported in this scope. Finally, the power quality (PQ) attributes like, input power factor (PF), total harmonic distortion (THD) over input current under stable and transient cases are disclosed to prove bettered PQ limits at the AC mains as prescribed by various IEEE-519 and IEC 61,000–3-2 standards.
Read full abstract