Open Core Protocol Research Articles

Verification of Open Core Protocol using System Verilog and UVM

The ever-increasing complexity of the integrated circuits design and the scale of the projects are making verification more challenging and time-consuming. As a result, the rapidly expanding VLSI industry necessitates a highly reliable and robust verification mechanism. In this paper, System Verilog Verification and Universal Verification Methodologies were adopted to verify the Accellera Open Core Protocol 3.0 as per specifications. According to the verification plan, the environment was developed under a dynamic approach, and the passive aspects included scoreboard, functional coverage, and system verilog assertions. The presented frameworks had verified OCP achieving successful dataflow signals extensions as per results.

Network on Chip Architecture for Multi-Agent Systems in FPGA

A system of interacting agents is, by definition, very demanding in terms of computational resources. Although multi-agent systems have been used to solve complex problems in many areas, it is usually very difficult to perform large-scale simulations in their targeted serial computing platforms. Reconfigurable hardware, in particular Field Programmable Gate Arrays devices, have been successfully used in High Performance Computing applications due to their inherent flexibility, data parallelism, and algorithm acceleration capabilities. Indeed, reconfigurable hardware seems to be the next logical step in the agency paradigm, but only a few attempts have been successful in implementing multi-agent systems in these platforms. This article discusses the problem of inter-agent communications in Field Programmable Gate Arrays. It proposes a Network-on-Chip in a hierarchical star topology to enable agents’ transactions through message broadcasting using the Open Core Protocol as an interface between hardware modules. A customizable router microarchitecture is described and a multi-agent system is created to simulate and analyse message exchanges in a generic heavy traffic load agent-based application. Experiments have shown a throughput of 1.6Gbps per port at 100MHz without packet loss and seamless scalability characteristics.

English

This paper gives a brief description of various on-chip bus protocols such as the Advanced Microcontroller Bus Architecture (AMBA) Advanced High-Performance bus (AHB) and Advanced Extensible Interface (AXI), Wishbone Bus, Open Core Protocol (OCP) and CoreConnect Bus. It gives a brief introduction of high performance system-on-chip bus protocol termed as the master-slave bus (MSBUS). By taking into consideration the inevitable trade-off among area, throughput and energy efficiency, the control bus is developed as low-cost and lowpower bus whereas the data bus is created as a high-throughput full-duplex bus. This on-chip bus protocol is differentiated from other on-chip bus protocols with feature of efficient block data transfer. This MSBUS is an effective bus protocol in many applications such as image processing, computer vision, and wireless communication where it requires less hardware resources and achieves higher performance, especially in block transfer mode. The comparison is made between different protocols with respect to various parameters.

On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions

Modern on-chip communication protocols such as advanced eXtensible interface and open core protocol support advanced transactions to improve communication efficiency. Out-of-order transactions that allow responses to be returned in an order different from their request order play an important role in this improvement. However, a deadlock situation may occur if these transactions are not properly manipulated. In this paper, we address the deadlock problem in an on-chip bus system supporting out-of-order transactions. We present a graphic model that can well represent the status of a bus system and show that a cycle exists in the graph if and only if the bus system is in an unsafe state that may lead to a bus deadlock. Based on this model, we propose a novel bus design technique that can efficiently resolve the bus deadlock problem. Experimental results show that buses with the proposed technique can be up to 3.3 times faster than those with the currently available techniques.

On-Chip Bus Designing with the Interface of Open Core Protocol

As more and more IP cores are integrated into an SOC design, the communication flow between IP cores has increased drastically and the efficiency of the on-chip bus has become a dominant factor for the performance of a system. The on-chip bus design can be divided into two parts, namely the interface and the internal architecture of the bus. In this work we adopt the well-defined interface standard, the Open Core Protocol (OCP), and focus on the design of the internal bus architecture. We develop an efficient bus architecture to support most advanced bus functionalities defined in OCP, including burst transactions, lock transactions, pipelined transactions, and out of-order transactions. We first model and design the on-chip bus with transaction level modeling for the consideration of design flexibility and fast simulation speed. We then implement the RTL models of the bus for synthesis and gate-level simulation. Experimental results show that the proposed TLM model is quite efficient for the whole system simulation and the real implementation can significantly save the communication time.

DESIGN OF ON-CHIP BUS OCP PROTOCOL WITH BUS FUNCTIONALITIES

The need for on-chip bus protocols are increased drastically for efficient and lossless communication among large number of IP cores of SOC design. This paper proposes a high-performance, highly scalable, busindependent interface between IP cores named as Open Core Protocol-International partnership. The Open Core Protocol (OCP) is a core centric point to point protocol which provides lossless communication and reduces design time, design risk, and manufacturing costs for SOC designs . Main property of OCP is that it can be configured with respect to the application required. The OCP is chosen because of its advanced supporting features such as configurable sideband control signaling and test harness signals, when compared to other core protocols. The OCP defines a pointto-point interface between two communicating entities such as IP cores and bus interface modules. One entity acts as the master of the OCP instance, and the other as the slave .In this paper, the most efficient bus architecture was adopted to support most advanced bus functionalities including simple transactions, burst transactions, pipelined transactions, and out-of-order transactions with respect to its suitable application in the real time product. The Open Core Protocol (OCP) was designed and the hardware modeling for that architecture was done using VHDL. This design is Simulated and Synthesized. An experimental result shows the efficiency of the proposed bus architecture and interface.

Monitoring transaction level SystemC models using a generic and aspect-oriented framework

Transaction level modelling (TLM) is gaining acceptance as a way to create hardware designs at high abstraction levels. It allows better simulation performances and early prototyping for system-on-chip (SoC) designs. Transaction level models are therefore increasingly being used as golden references. In this paper, we present a new framework for the verification of properties of SystemC transaction level models during simulation. Functional as well as performance properties are addressed. Aspect-oriented programming (AOP) techniques are exploited to monitor the design under verification in an automated way and to write assertion checkers that fit TLM requirements. In addition, we propose a generic SystemC implementation approach that allows the specification and validation of fully-parameterisable transaction level properties. We illustrate our work on a realistic multi-level SoC platform based on the TLM-2.0 standard and including Open Core Protocol (OCP) interfaces.

Provably correct on-chip communication

Hardware module reuse is a standard solution to the problems of increasing complexity of chip architectures and pressure to reduce time to market. In the absence of a single module interface standard, predesigned modules for “plug-and-play” usually require a converter between incompatible interface protocols. Current approaches to automatic synthesis of protocol converters mostly lack formal foundations and either employ abstractions far removed from the HDL implementation level or grossly simplify the structure of the protocols considered. This work presents a state-machine-based formalism for modeling bus-based communication protocols and a notion of protocol compatibility and of correct conversion between incompatible protocols. This formalism is used to derive algorithms for checking protocol compatibility and for provably correct, automatic converter synthesis. Experiments with automatic converter synthesis between different configurations of widely used commercial bus protocols, such as AMBA AHB, ASB APB, and the Open Core Protocol (OCP) are discussed. The work here is unique in its combination of a completely formal approach and the use of a low abstraction level that enables precise modeling of protocol characteristics that is also close to HDL.

Overview of Debug Standardization Activities

This article presents an overview of the goals and activities of five debug standardization bodies: the Nexus 5001, MIPI (Mobile Industry Processor Interface) Test and Debug, IEEE P1149.7, IEEE P1687, and OCP-IP (Open Core Protocol International Partnership) Debug working groups. The article also describes the relation between these various activities and discusses their standardization plans for the near future.

Implementation of guaranteed services in the MANGO clockless network-on-chip

Shared, segmented, on-chip interconnection networks, known as networks-on-chip (NoC), may become the preferred way of interconnecting intellectual property (IP) cores in future giga-scale system-on-chip (SoC) designs. A NoC can provide the required communication bandwidth while accommodating the effects of scaling microchip technologies. Equally important, a NoC facilitates a truly modular and scalable design flow. The MANGO (message-passing asynchronous network-on-chip providing guaranteed services over open core protocol (OCP) interfaces) NoC is presented, and how its key characteristics (clockless implementation, standard socket access points, and guaranteed communication services) make MANGO suitable for a modular SoC design flow is explained. Among the advantages of using clockless circuit techniques are inherent global timing closure, low forward latency in pipelines, and zero dynamic idle power consumption. Time division multiplexing, generally used to provide bandwidth guarantees in clocked NoCs, however, is not possible in a clockless environment. MANGO provides an alternative, high-performance solution to providing hard, connection-oriented service guarantees, using clockless circuit techniques. In-depth circuit details are presented, and the 0.13 µm standard cell implementation of a 5×5 routing node, for use in a mesh type NoC, is described.