On-line Testing Techniques Research Articles

Adaptive BIST for Concurrent On-Line Testing on Combinational Circuits

Safety-critical systems embedding concurrent on-line testing techniques are vulnerable to design issues causing the degradation of totally self-checking (TSC) property, which is proved to be fatal for further operations (e.g., space electronics, medical devices). In addition to the exploration of the degradation of TSC property over time, a concurrent on-line testing architecture is offered that adjusts the input activity, addressing the absence of input values or the low frequency of their appearance (e.g., during sleep mode). During concurrent on-line testing, the inputs of the circuit under test (CUT) are, at the same time, its test vectors. This architecture tolerates possible degradation of the terms that contribute to the calculation of the totally self-checking goal (TSCG(t)). An adaptive built-in self-test (BIST) unit is proposed that dynamically applies test vector subsets when permitted, based on the frequency of appearance of the input values. The clustering of the inputs is based on the k-means algorithm and, in combination with the ordering of the test vectors to minimize the subsets, results in partitioning the test procedure in a significantly shorter time. The comparison to other solutions used for concurrent on-line testing showed that the proposed adaptive BIST has significant advantages. It can cope with rare occurrences, or even no occurrence, of input values by enabling the BIST mechanism appropriately. The results showed that it may increase the TSCG(t) up to almost 90% when applied during a low-power mode and present better concurrent test latency (CTL) when assumptions regarding the availability of all input values and the probability of occurrence are not realistic.

Detecting Emotion in Speech: Validating a Remote Assessment Tool

ABSTRACT Recent global events have called for the development of online testing and evaluation techniques, for both clinical and research purposes. Online testing is especially important for older adults who might have limited access to health services due to mobility difficulties or health risks. The current study aimed to validate an online tool, Internet-based Test for Rating of Emotions in Speech (iT-RES), designed to test the perception of emotions in spoken language and assess its efficacy as a remote telehealth assessment tool for older adults. Forty-one older adults (age 60–80) and 44 young adults (age 20–29) performed the online iT-RES. Age-related differences in the online tool were compared with respective age-related effects in a parallel lab-based tool. The three main age-related effects found in the lab-based version were replicated in the iT-RES online version. (1) Better identification of emotion by young adults; (2) Failures of Selective Attention were larger for older adults; (3) Older adults gave lower weight to the prosodic channel as compared to younger adults. Our findings add to the growing body of literature regarding the validity of online neuropsychological assessment. We also present and discuss several measures taken to ensure quality online testing and increase overall test validity.

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

The highly parallel processing capabilities and reduced power performance of General Purpose Graphics Processing Units (GPGPUs) have been crucial factors for their massive use in multiple fields, such as multimedia and high-performance computing applications. Nowadays, more demanding areas, such as automotive, employ GPGPU devices where safety and reliability are mandatory design constraints. Nevertheless, the structural complexity, the transistor density, and the implementation in the latest silicon technologies introduce challenges to match safety and reliability requirements. In these technologies, wear-out and aging are factors that may significantly increase the occurrence of permanent faults during the lifetime operation. Moreover, these faults may generate unacceptable misbehaviors during the execution of an application. These constraints require devising new methods for in-field fault detection, thus verifying the integrity and correct behavior of the device during its whole operational life. This work proposes a technique to generate functional self-test programs targeting the detection of permanent static faults in the memory of the warp scheduler of a GPGPU. The proposed technique can translate fault primitives, which represent the effect of faults in a memory cell, into self-test functions and programs composed of a sequence of operations to excite the fault in the memory and to propagate its effects to a visible location, thus detecting its presence. We focused on the memory in the warp scheduler because it represents a crucial module for the device operation. Furthermore, this memory is present in each Streaming Multiprocessor (SM) of a GPGPU. Some experimental results to validate the method have been gathered, resorting to the NVIDIA Visual Profiler and the Nsight Debugger using the NVIDIA-GEFORCE GTX GPU platform and a structural fault simulator. The CUDA programming environment was used to implement the test procedures.

Application Model of Learning B-O-R-N With Moodle Basic For Improving Student Learning Result in Operating System

<p>This research is Classroom Action Research (CAR) by using B-O-R-N model based on moodle Each cycle consists of planning stage, action implementation stage, observation stage, and reflection phase. Subjects in this classroom action research were class X students RPL A SMK Negeri 2 Karanganyar academic year 2016/2017 with the number of learners 36 learners. Data collection was done by using documentation techniques, interview techniques, online test techniques and group discussion results. The observed aspects consist of cognitive, affective and psychomotor aspects. Data analysis technique used is descriptive comparative. Compare students' work results by using percentage figures. The results obtained as follows: 1) achievement of cognitive aspects on precycle 38.89% in the first cycle increased 52.79% and again increased in the second cycle of 77.78%. 2) achievement of affective aspect on precycle = 19,44%, cycle I = 61,11%, and cycle II = 86,11%. 3) psychomotor aspect achievement on precycle = 41.67%, cycle I = 69.44%, cycle II = 83.33%. Based on the result of the research, it can be concluded that the learning model of B-O-R-N assisted by moodle media is effective in improving learners' learning outcomes in the subject matter of administration of open source operating system class X RPL A SMK Negeri 2 Karanganyar periode 2016/2017.</p>

Mobolic: An automated approach to exercising mobile application GUIs using symbiosis of online testing technique and customated input generation

SummaryThe increasingly prevalent use of mobile devices has raised the popularity of mobile applications. Therefore, automated testing of mobile applications has become an extremely important task. However, it is still a challenge to automatically generate tests with high coverage for mobile applications due to their specific nontrivial structure and the highly interactive nature of graphical user interfaces (GUIs). In this paper, we propose a novel automated GUI testing technique for mobile applications, namely, Mobolic. In this approach, tests with high coverage are automatically generated and executed by combining the online testing technique and customated input generation. Employing the online testing technique, Mobolic systematically explores the app GUI without falling in a loop. It generates relevant events “on the fly” that are followed by an immediate execution. In addition, involving the customated input generation, Mobolic automatically generates relevant user inputs such as user‐predefined, concrete, or random ones. We implemented Mobolic and evaluated its performance on 10 real‐world open‐source Android applications. Our experimental results show the effectiveness and efficiency of Mobolic in terms of achieved code coverage and overall exercising time.

Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs

As technology scales, the increased vulnerability of modern systems due to unreliable components becomes a major problem in the era of multi-/many-core architectures. Recently, several on-line testing techniques have been proposed, aiming towards error detection of wear-out/aging-related defects that can appear during the lifetime of a system. In this work, firstly we investigate the relation between system test latency and test-time overhead in multi-/many-core systems with shared Last-Level Cache (LLC) for periodic Software-Based Self-Testing (SBST), under different test scheduling policies. Secondly, we propose a new methodology aiming to reduce the extra overhead related to testing that is incurred as the system scales up (i.e., the number of on-chip cores increases). The investigated scheduling policies primarily vary the number of cores concurrently under test in the overall system test session. Our extensive, workload-driven dynamic exploration reveals that there is an inverse relationship between the two test measures; as the number of cores concurrently under test increases, system test latency decreases, but at the cost of significantly increased test time, which sacrifices system availability for the actual workloads. Under given system test latency constraints, which dictate the recovery time in the event of error detection, our exploration framework identifies the scheduling policy under which the overall test-time overhead is minimized and, hence, system availability is maximized. For the evaluation of the proposed techniques, multi-/many-core systems consisting of 16 and 64 cores are explored in a full-system, execution-driven simulation framework running multi-threaded PARSEC workloads.

First Steps in Creating Online Testable Reversible Sequential Circuits

Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented using quantum dot cellular automata. Other work has used traditional designs for sequential circuits and replaced the flip-flops and the gates with their reversible counterparts. Our earlier work uses a direct feedback method without any flip-flops, improving upon the replacement technique in both quantum cost and ancilla inputs. We present here a further improved version of the direct feedback method. Design examples show that the proposed method produces better results than our earlier method in terms of both quantum cost and ancilla inputs. We also propose the first technique for online testing of single line faults in sequential reversible circuits.

A general framework for comparing automatic testing techniques of Android mobile apps

Abstract As an increasing number of new techniques are developed for quality assurance of Android applications (apps), there is a need to evaluate and empirically compare them. Researchers as well as practitioners will be able to use the results of such comparative studies to answer questions such as, “What technique should I use to test my app?” Unfortunately, there is a severe lack of rigorous empirical studies on this subject. In this paper, for the first time, we present an empirical study comparing all existing fully automatic “online” testing techniques developed for the Android platform. We do so by first reformulating each technique within the context of a general framework. We recognize the commonalities between the techniques to develop the framework. We then use the salient features of each technique to develop parameters of the framework. The result is a general recasting of all existing approaches in a plug-in based formulation, allowing us to vary the parameters to create instances of each technique, and empirically evaluate them on a common set of subjects. Our results show that (1) the proposed general framework abstracts all the common characteristics of online testing techniques proposed in the literature, (2) it can be exploited to design experiments aimed at performing objective comparisons among different online testing approaches and (3) some parameters that we have identified influence the performance of the testing techniques.

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

This brief proposes an on-line transparent test technique for detection of latent hard faults which develop in first-input first-output buffers of routers during field operation of NoC. The technique involves repeating tests periodically to prevent accumulation of faults. A prototype implementation of the proposed test algorithm has been integrated into the router-channel interface and on-line test has been performed with synthetic self-similar data traffic. The performance of the NoC after addition of the test circuit has been investigated in terms of throughput while the area overhead has been studied by synthesizing the test hardware. In addition, an on-line test technique for the routing logic has been proposed which considers utilizing the header flits of the data traffic movement in transporting the test patterns.

A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures

Aggressive technology scaling triggers novel challenges to the design of multi-/many-core systems, such as limited power budget and increased reliability issues. Today's many-core systems employ dynamic power management and runtime mapping strategies trying to offer optimal performance while fulfilling power constraints. On the other hand, due to the reliability challenges, online testing techniques are becoming a necessity in current and near future technologies. However, state-of-the-art techniques are not aware of the other power/performance requirements. This paper proposes a power-aware non-intrusive online testing approach for many-core systems. The approach schedules software based self-test routines on the various cores during their idle periods, while honoring the power budget and limiting delays in the workload execution. A test criticality metric, based on a device aging model, is used to select cores to be tested at a time. Moreover, power and reliability issues related to the testing at different voltage and frequency levels are also handled. Extensive experimental results reveal that the proposed approach can i) efficiently test the cores within the available power budget causing a negligible performance penalty, ii) adapt the test frequency to the current cores' aging status, and iii) cover available voltage and frequency levels during the testing.

The Research on the Form Error Margin of the Auto Test System Design

In the machine manufacture industry, the on-line test technique applies very extensively, the particularly automatic test technique is more outstanding. This article with the form error margin for example, designed a set of simple on-line test system to raise the accuracy of the machine product examination, assurance product quality, decline low cost depletion.

Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs

System test and online test techniques are aggressively being used in today’s SoCs for improved test quality and reliability (e.g., aging/soft-error robustness). With gaining popularity of vertical integration such as 2.5D and 3D, in the semiconductor industry, ensuring thermal safety of SoCs during these test modes poses a challenge. In this paper, we propose a dynamic test scheduling mechanism for system tests and/or online test that uses dynamic feedback from on-chip thermal sensors to control temperature during shift (or scan) and capture, thereby ensuring thermal-safe conditions while applying the test patterns. The proposed technique is a closed loop test application scheme that eliminates the need for separate thermal simulation of test patterns at design stage. The technique also enables granular field-level configuration of thermal limits, so that different units across multiple cores are subjected to customized thermal profiles. Results from implementation of the proposed schemes on a 4-layer, 16-core, 12.8 million gates, OpenSparc S1 processor subsystem are presented.

Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors

As the semiconductor industry continues its relentless push for nano-CMOS technologies, long-term device reliability and occurrence of hard errors have emerged as a major concern. Long-term device reliability includes parametric degradation that results in loss of performance as well as hard failures that result in loss of functionality. It has been reported in the ITRS roadmap that effectiveness of traditional burn-in test in product life acceleration is eroding. Thus, to assure sufficient product reliability, fault detection and system reconfiguration must be performed in the field at runtime. Although regular memory structures are protected against hard errors using error-correcting codes, many structures within cores are left unprotected. Several proposed online testing techniques either rely on concurrent testing or periodically check for correctness. These techniques are attractive, but limited due to significant design effort and hardware cost. Furthermore, lack of observability and controllability of microarchitectural states result in long latency, long test sequences, and large storage of golden patterns. In this paper, we propose a low-cost scheme for detecting and debugging hard errors with a fine granularity within cores and keeping the faulty cores functional, with potentially reduced capability and performance. The solution includes both hardware and runtime software based on codesigned virtual machine concept. It has the ability to detect, debug, and isolate hard errors in small noncache array structures, execution units, and combinational logic within cores. Hardware signature registers are used to capture the footprint of execution at the output of functional modules within the cores. A runtime layer of software (microvisor) initiates functional tests concurrently on multiple cores to capture the signature footprints across cores to detect, debug, and isolate hard errors. Results show that using targeted set of functional test sequences, faults can be debugged to a fine-granular level within cores. The hardware cost of the scheme is less than three percent, while the software tasks are performed at a high-level, resulting in a relatively low design effort and cost.

Microarchitectural Online Testing for Failure Detection in Memory Order Buffers

Technology scaling leads to burn-in phase out and higher postsilicon test complexity, which increases in-the-field failure rate due to both latent defects and actual errors, respectively. As a consequence, current reliability qualification methods will likely be infeasible. Microarchitecture knowledge of application runtime behavior offers a possibility to have low-cost continuous online testing techniques detect hard errors in the field. Whereas data can be protected with redundancy (like parity or ECC), there is a lack of mechanism for control logic. This paper proposes a microarchitectural approach for validating that the memory order buffer logic works correctly. Our design relies on a small cache-like structure that keeps track of the last store to each cached address. Each load is checked to have obtained the data from the youngest older producing store. We present three different implementations of this idea, offering different trade-offs for error coverage, performance overhead, and design complexity.

Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips

Microfluidics-based biochips are soon expected to revolutionize biosensing, clinical diagnostics and drug discovery. Robust off-line and on-line test techniques are required to ensure system dependability as these biochips are deployed for safety-critical applications. Due to the underlying mixed-technology and mixed-energy domains, biochips exhibit unique failure mechanisms and defects. We first relate some realistic defects to fault models and observable errors. We next set up an experiment to evaluate the manifestations of electrode-short faults. Motivated by the experimental results, we present a testing and diagnosis methodology to detect catastrophic faults and locate faulty regions. The proposed method is evaluated using a biochip performing real-life multiplexed bioassays.

Ultra low-cost defect protection for microprocessor pipelines

The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing defects, are a growing challenge that threatens the yield and product lifetime of future systems. In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects. To achieve this goal we combine area-frugal on-line testing techniques and system-level checkpointing to provide the same guarantees of reliability found in traditional solutions, but at much lower cost. Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity of the underlying hardware. In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode. Using detailed circuit-level and architectural simulation, we find that our approach provides very high coverage of silicon defects (89%) with little area cost (5.8%). In addition, when a defect occurs, the subsequent degraded mode of operation was found to have only moderate performance impacts, (from 4% to 18% slowdown).

Ultra low-cost defect protection for microprocessor pipelines

The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing defects, are a growing challenge that threatens the yield and product lifetime of future systems. In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects. To achieve this goal we combine area-frugal on-line testing techniques and system-level checkpointing to provide the same guarantees of reliability found in traditional solutions, but at much lower cost. Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity of the underlying hardware. In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode. Using detailed circuit-level and architectural simulation, we find that our approach provides very high coverage of silicon defects (89%) with little area cost (5.8%). In addition, when a defect occurs, the subsequent degraded mode of operation was found to have only moderate performance impacts, (from 4% to 18% slowdown).

Ultra low-cost defect protection for microprocessor pipelines

The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing defects, are a growing challenge that threatens the yield and product lifetime of future systems. In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects. To achieve this goal we combine area-frugal on-line testing techniques and system-level checkpointing to provide the same guarantees of reliability found in traditional solutions, but at much lower cost. Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity of the underlying hardware. In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode. Using detailed circuit-level and architectural simulation, we find that our approach provides very high coverage of silicon defects (89%) with little area cost (5.8%). In addition, when a defect occurs, the subsequent degraded mode of operation was found to have only moderate performance impacts, (from 4% to 18% slowdown).

Online test using displacement-force mixed control

This paper proposes an online test technique that employs mixed control of displacement and force. Two types of mixed control, ‘displacement–force combined control’ and ‘displacement–force switching control’ are proposed. In displacement–force combined control, one jack is operated by displacement-control, and another is operated by force-control. Validity of the combined control technique is demonstrated by a series of online tests applied to a base-isolated structure subjected to horizontal and vertical ground motions simultaneously. The substructuring technique is employed in the tests, and the base-isolation layer is tested, with the rest of the structure modeled in the computer. Displacement-control and force-control were adopted for simulating the horizontal and vertical response, respectively. Both displacement- and force-control were implemented successfully despite interference between the two jacks. Earthquake responses of the base-isolated structure involving the effects of varying axial forces on the horizontal hysteretic behavior of the base-isolation layer were simulated. In the displacement–force switching control, the jack was operated by displacement-control when the test specimen was flexible but switched to force-control once the specimen became stiff. Validity of the switching control technique was also checked by a series of online tests applied to the base-isolated structure subjected to vertical ground motions. Switching between displacement-control and force-control was achieved when the axial force applied to the base-isolation layer changed from tension to compression or from compression to tension. Both the displacement- and force-control were successful even with many rounds of switching. The test revealed that large accelerations occurred on the floor immediately above the base-isolation layer at the instants when the axial force of the base-isolation layer changed from tension to compression. Copyright © 2005 John Wiley & Sons, Ltd.

Online testing approach for very deep-submicron ICs

Very deep-submicron technologies pose new challenges to IC testing. In particular, crosstalk and transient faults are difficult to detect with traditional methods. Online testing techniques can detect these faults, however, and a new approach extends these techniques to include gross-delay faults. Moreover, this approach described by the authors can be exploited to detect stuck-at and bridging faults offline.