One-tap Decision Feedback Equalizer Research Articles

A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS

This article presents a 56-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter/receiver (TX/RX) chipset for optical link. The optical transmitter (TX) adopts a digital-to-analog converter (DAC)-based structure with a two-tap nonlinear PAM-4 feed-forward equalizer (FFE) implemented in the digital domain to compensate for the asymmetric responses from the vertical cavity surface-emitting laser (VCSEL). The 56-Gb/s PAM-4 receiver (RX) is connected to the photodiode (PD) and transimpedance amplifier (TIA) module for optical application. The interconnection loss from the RX chip to the PD+TIA module is compensated by the RX continuous-time linear equalizer (CTLE) and the one-tap decision-feedback equalizer (DFE). The pattern-filter-based bang-bang phase detector in the RX improves the jitter performance. Both TX and RX are fabricated in the 40-nm CMOS. The VCSEL TX demonstrates a 56-Gb/s compensated PAM-4 waveform with −0.9-dBm outer optical modulation amplitude (OMA) while consuming only 97 mW of power (1.73 pJ/b). The RX achieves 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> bit error rate (BER) with 0.08 UI margin under 10-dB interconnection loss while dissipating 278 mW of power (4.96 pJ/b).

A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC

A time-interleaved duobinary encoding scheme for the low-power high-bandwidth memory (HBM) I/O interface is proposed with a 65-nm CMOS process. To reduce power consumption in HBM I/O using multiple through-silicon via (TSV) I/Os, a transmitter (TX) that performs duobinary signaling with a voltage-mode driver is proposed. A small area encoder is implemented to generate duobinary output and an edge-boosted pre-driver is proposed to improve the slew rate and the robustness against the process, voltage, and temperature (PVT) variations of the duobinary voltage-mode driver. To convert the duobinary signal into a non-return-to-zero (NRZ) signal, a one-tap decision feedback equalizer (DFE) is used at the receiver (RX). NRZ signal conversion is proposed using one reference voltage and one PMOS switch to reduce the hardware complexity caused by additional reference voltages. An eight-stacked TSV is emulated in the 65-nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency of the proposed transceiver chip is 0.373 pJ/b/pF with a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> – 1 pseudorandom binary sequence at 5 Gb/s.

A Wide-Range FD for Referenceless Baud-Rate CDR Circuits

A wide-range frequency detector (FD) is presented for baud-rate clock and data recovery (CDR) circuits. It achieves a wide frequency capture range, a short lock time, and a low power. By using this FD, a referenceless quarter-rate CDR circuit with a one-tap decision feedback equalizer is fabricated in 40-nm CMOS technology. The active area of this CDR circuit is 0.0999mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and its power is 44mW while the data rate is 16.8Gbps. The calculated energy efficiency of this CDR circuit is 2.62pJ/b.

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

An 8.5-Gb/s/pin (Gb/s) 12-Gb LPDDR5 SDRAM is implemented in a second-generation 10-nm DRAM process with a hybrid-bank architecture that provides a power-optimized bank solution depending on the bank modes (4B/4BG, 16B-merged bank, 8B-split bank). Based on the specified bank modes, vertical and horizontal skew-cancel schemes for high density and an RBUS-based DBI ac to minimize data transition are newly proposed. Thus, the switching power of RBUS DBI ac is saved by 8.9% compared to that of DBI ac “OFF.” To improve the rank interleaving efficiency with a current increase, partially enabled WCK (PE-WCK) mode is proposed, which minimizes the number of enabled circuits for maintaining the WCK2CK synchronization. Therefore, the current can be saved by 62% without a timing constraint compared to the WCK always-ON mode. To achieve high-speed operation beyond 6.4 Gb/s, speed-boosting techniques, namely, the two-step duty corrector, active resonant load (ARL), and one-tap decision feedback equalizer (DFE) with offset calibration, are newly adopted. In the coarse step in the two-step duty corrector, the value of the duty error decreases to below 5% by suppressing the dc signal. In the fine step, the remaining duty error is further reduced within 2.5 ps by the duty cycle monitor (DCM) and duty cycle adjustor (DCA). Moreover, the skew increase beyond 6.4 Gb/s due to the bandwidth limit by the heavy loading of four-phase WCK signals is alleviated by the ARL, where the four-phase skew is within 5 ps irrespective of process, voltage, and temperature (PVT) variations. The direct feedback DFE enables fast feedback (<; 118 ps) for tap coefficient control, and offset calibration reduces the three-sigma offset of the four dynamic latches in DQ within 5 mV.

A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET

The design of a dual-mode, 19-58-Gb/s four-level pulse-amplitude modulation (PAM-4) and 9.5-29-Gb/s nonreturn to zero (NRZ), transceiver in 16-nm FinFET is presented. The fully adaptive receiver consists of a multi-stage continuous time linear equalizer (CTLE), a configurable 32-way time-interleaved 3-to-7-bit successive-approximation-register (SAR) analog to digital converter (ADC), a 14-tap feed forward equalizer (FFE)/one-tap decision feedback equalizer (DFE) digital signal processing (DSP), and a baud-rate clock and data recovery (CDR). A four-tap voltage mode transmitter with two pre-cursor taps and one post-cursor tap, incorporates impedance control loop to meet return loss requirements while maintaining good PAM-4 level mismatch ratio of 0.98. At 56 Gb/s, the transceiver achieves the <;1e-12 bit error rate (BER) without explicitly added crosstalk, <;1e-6 BER with 2 mVrms (crest-factor of 10) additional crosstalk, over a 32-dB channel while consuming 9.7 pJ/bit with 7-bit ADC. The transceiver equalizes channel losses up to 46 dB with pre-forward error correction BER <;1e-5 at 58 Gb/s without additional crosstalk. With 3-bit ADC, it achieves 6.4 pJ/bit over a clean 7.4-dB channel.

A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS

This paper presents a referenceless baud-rate clock and data recovery (CDR) incorporated with a continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) to achieve data rates from 22.5 to 32 Gb/s across a channel with Nyquist loss ranging from 10.1 to 14.8 dB. The referenceless CDR includes a proposed frequency acquisition scheme that consists of two parts: frequency detection and frequency correction. Frequency detection is achieved by examining rising and falling data waveforms to detect discrepancies between the data rate and the locally recovered clock frequency. Frequency correction uses digitally adjustable asymmetry of the proposed adjustable baud-rate phase detector to correct any frequency error. The receiver is implemented in the TSMC 28-nm CMOS process with an analog front end consisting of a CTLE, sampling comparators, a digitally controlled oscillator, and a digital back end consisting of synthesized digital CDR logic. The open-loop frequency detector range is measured to be 39%. The closed-loop CDR capture range is measured to be 34%, limited by test equipment. The proposed frequency acquisition scheme improves the measured CDR capture range by up to 227×. At 32 Gb/s, the entire receiver consumes 102.04 mW, achieving energy consumption below 3.19 pJ/b.

A DC-to-12.5 Gb/s 9.76 mW/Gb/s All-Rate CDR With a Single &lt;italic&gt;LC&lt;/italic&gt; VCO in 90 nm CMOS

A dual-lane DC-to-12.5 Gb/s all-rate clock and data recovery (CDR) IC with a single LC voltage-controlled oscillator is fabricated in a 90 nm CMOS. An all-rate clock divider with an asynchronous phase calibration scheme is employed to generate all-rate clock signals without a phase mismatch or duty cycle distortion. The IC features an automatic loop gain control scheme that adjusts the bandwidth of a CDR in the background for optimal bit error rate (BER) performance by monitoring the phase difference between the incoming data and the recovered clock signal. The proposed CDR consumes 244 mW at 12.5 Gb/s under dual-lane operation with an input sensitivity of 12 mVpp,diff. The CDR supports referenceless allrate operation with a BER <; 10 -12 on PRBS31 and compensates for 20 dB of channel loss using a continuous-time linear equalizer (CTLE), a one-tap decision feedback equalizer (DFE), and a three-tap pre-emphasis filter. The power efficiency of the test chip is 9.76 mW/Gb/s.

A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor

This paper describes a 28-Gb/s receiver IC with self-contained adaptive equalization and sampling point control using an on-chip stochastic sigma-tracking eye-opening monitor (SSEOM). The proposed SSEOM accurately detects the bit-error-rate (BER)-related eye contour efficiently without the use of an external microcontroller. The SSEOM determines the BER-optimal sampling point and equalizer coefficients on the basis of pattern-filtered eye diagrams. It also features a background adaptation scheme for robust long-term operation by tracking temperature variations and device aging. The proposed SSEOM is integrated in a 28-Gb/s receiver that is designed to compensate for channel loss up to 25 dB at the Nyquist rate by using a continuous time linear equalizer (CTLE) and a one-tap decision feedback equalizer (DFE) together with an one-tap pre-emphasis at a transmitter. The time required for complete adaptation and the total power consumption are 364 ms and 43.9 mW, respectively. The proposed 28-Gb/s receiver is fabricated in 40 nm CMOS.

A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

This brief presents an adaptive continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB method is extended for not only CTLE but also DFE with the aid of gain characteristics of one-tap DFE. Thus, adaptation loops for each equalizer type are merged to a single loop. As a result, the complexity and power consumption of the adaptation circuits are reduced significantly. The test chip consumes 34.2 mW from 1.2 V supply with 65-nm CMOS process.

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay- and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mV $_{\rm ppd}$ to 1.06 V $_{\rm ppd}$ . RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10 $^{-12}$ is 42 mV $_{\rm ppd}$ . The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10 $^{-15}$ on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection

A 10-Gb/s adaptive parallel receiver with joint crosstalk canceller (XTC) and decision-feedback equalizer (DFE) is presented. A differentiator-based XTC and a one-tap DFE are adapted to cancel far-end crosstalk (FEXT) and inter-symbol interference (ISI), respectively. When the lengths of the coupled microstrip lines change, an FEXT detector measures and compares the powers of FEXT and XTC to digitally update the XTC coefficient. Then, an ISI detector measures and compares the powers of the received data and recovered data to digitally update the DFE coefficient. This adaptive parallel receiver was fabricated in a 40-nm CMOS technology. The maximum power consumption is 17.55 mW from a 1.3-V supply, and the core area occupies 0.0352 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . For a 10-Gb/s PRBS of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> -1 passing through 15-in FR4 printed-circuit-board traces with 8-mil spacing, the measured rms and peak-to-peak jitter of recovered data are 5.56 and 30.2 ps, respectively. The measured bit error rate is less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . The measured total calibration time is 2.424 μs.

Decision Feedback Equalizers Using the Back-Gate Feedback Technique

A merged adder/D-type flip-flop (DFF) is presented by using the back-gate feedback technique. By using this merged adder/DFF, a slicerless one-tap decision feedback equalizer (DFE) and a cascaded DFE are fabricated in 65-nm CMOS technology. For a cable loss of 12 dB and a 30-Gb/s pseudorandom bit sequence (PRBS) of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> - 1, the measured bit error rate of the slicerless one-tap DFE is below 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-11</sup> . Its power dissipation is 27 mW from a 1-V supply. For a cable loss of 12 dB and a 30-Gb/s PRBS of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> - 1, the measured bit error rate of the cascaded DFE is below 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . This cascaded DFE consumes 55 mW from a 1-V supply.

Bandwidth-efficient wireless OFDM

Due to ever-increasing bandwidth demands in future wireless service, the radio frequency band becomes more and more invaluable. In this paper, we address channel equalization for bandwidth-efficient wireless orthogonal frequency-division multiplexing (OFDM). First, we show that in order to be free of both interchannel interference and interblock interference, wireless OFDM has to occupy a bandwidth wider than the Nyquist rate and use insufficient statistics in symbol demodulation. Thus, the conventional OFDM gains computational efficiency using the discrete Fourier transform (DFT) in demodulation at the cost of low efficiency of bandwidth usage and degradation in symbol error performance. Then we consider the OFDM that achieves high efficiency of bandwidth usage, allows interchannel interference and interblock interference to exist, and uses sufficient statistics in symbol demodulation. A one-tap decision feedback equalizer (DFE) is proposed for equalization of the bandwidth efficient OFDM system. Simulation and numerical evaluation for an indoor wireless asynchronous transfer mode network are carried out. It is demonstrated that though occupying a narrower bandwidth, the one-tap DFE-based bandwidth-efficient OFDM system achieves lower symbol error rate and higher mutual information than the conventional DFT-based OFDM system. The proposed OFDM system presents a monotonically increasing symbol error rate, and convex-down achieved mutual information with respect to increasing efficiency of bandwidth usage.

The autocorrelation of error propagation in a one-tap decision-feedback equalizer

The autocorrelation function of error propagation for a one-tap decision-feedback equalizer is derived. The autocorrelation is shown to be a geometric sequence which may or may not have alternating sign depending on the channel impulse response. >