One-hot Residue Research Articles

Design and analysis of dual-mode numerically controlled oscillators based controlled oscillator frequency modulation

In this paper, the design and analysis of dual-mode numerically controlled oscillators (NCO) based controlled oscillator frequency Modulation is implemented. Initially, input is given to the analog to digital (ADC) converter. This will change the input from analog to digital converter. After that, the pulse skipping mode (PSM) logic and proportional integral (PI) are applied to the converted data. After applying PSM logic, data is directly transferred to the connection block. The proportional and integral block will transfer the data will be decoded using the decoder. After decoding the values, it is saved using a modulo accumulator. After that, it is converted from one hot residue (OHR) to binary converter. The converted data is saved in the register. Now both data will pass through the gate driver circuit and output will be obtained finally. From simulation results, it can observe that the usage of metal oxide semiconductor field effect transistors (MOSFETs) and total nodes are very less in dual-mode NCO-based controlled oscillator frequency modulation.

Static register implementation for one hot residue number systems

A method of implementing static registers for one-hot residue number systems is described. The method overcomes the high power dissipation problems associated with conventional flip-flops and clock distribution. The proposed design relies on the low activity factor inherent in the one hot coding structure and a hybrid clocking system that minimises the switching capacitance associated with the clock distribution.

PN code generator with low delay-power product for spread-spectrum communication systems

We illustrate the low-power advantages of the One-Hot Residue Number System by presenting a pseudonoise (PN) code generator for battery-powered spread-spectrum communication systems. It exhibits a significantly reduced delay-power product below an equivalent binary number system implementation. This advantage is obtained because the number system allows the decomposition into small serially enabled units of the large linear-feedback shift register required to generate the PN code. Additionally, it allows fast and efficient computation of sums and products. An example frequency-hopped spread-spectrum application of the generator is briefly presented using a previously designed frequency synthesizer.

Delta-sigma modulator with large OSR using the one-hot residue number system

A digital delta-sigma modulator using the one-hot residue number system (OHRNS) is presented. It exhibits a large oversampling ratio (OSR) in comparison with equivalent binary designs. Its second-order architecture employs a two-stage cascade structure with two-level internal and four-level output quantization. It is intended for use in a high-resolution interpolative digital-to analog converter. Analytical estimates show a significant improvement in OSR and latency over binary-number system-based designs. These benefits are made possible by the use of the (OHRNS), which allows addition and multiplication to be performed equally quickly and simply, using barrel shifters and signal transposition. An application specific integrated circuit (ASIC) implementation of the design is also presented in a 2-/spl mu/m CMOS technology.

One-hot residue coding for low delay-power product CMOS design

CMOS implementations of arithmetic circuits for One-Hot Residue (OHR) encoded operands are presented. They are shown to possess SPICE-simulated delay-power (DP) products that are significantly reduced below those of their binary number system counterparts (ripple-carry adder and Wallace tree multiplier). The reduction is attributable to the one-hot representation, which decreases the number of critical path transistors and signal activity factors. An OHR-based direct digital frequency synthesizer for frequency-hopped communication systems is presented, and analytical estimates of its DP-product are derived. The design exhibits a DP-product reduction in excess of 90% below that of a binary-encoded residue synthesizer.