On-chip Voltage Reference Research Articles

Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator

This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CVREF2 switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.

A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC

This paper presents a 12-b, 1-GS/s ADC array, realized by time-interleaving four 250-MS/s pipelined SAR ADCs, with integrated on-chip reference voltage buffers. A reference ADC-based calibration algorithm treats static nonlinearity, gain, and offset errors in the array. Timing-skew errors between the sub-ADCs are distinguished from those of the gain mismatches by the assistance of an analog high-pass filter (HPF) for input slope information and subsequently corrected by digitally controlled delay lines (DCDLs). Directly driven off the on-chip 50- $\Omega $ termination resistors without any dedicated input buffer, the 65-nm CMOS prototype ADC array also employs a frequency-hopped, randomly-sampling scheme for the ref. ADC, eliminating the spectral effect of its interference to the main array. The core ADC consumes 31.5 mW and occupies an area of 0.27 mm2, including nine on-chip reference voltage buffers, the ref. ADC, and the HPF path. The measured peak signal to noise and distortion ratio of the array is 65.3 dB, and the measured spurious-free dynamic range is >70 dB from dc to 500 MHz at 1 GS/s with calibration. The prototype ADC chip achieves an figure of merit of 20.9 and 59.7 fJ/step (the latter is limited by the jitter of an off-chip clock source) for a low-frequency input and a Nyquist input, respectively.

A 700-MS/s 6-bit SAR ADC with partially active reference voltage buffer

This paper presents a 700-MS/s 6-bit SAR ADC with a novel on-chip reference voltage buffer in a 40-nm CMOS Low-Leakage (LL) process. The reference voltage buffer is partially active depending on the operation state of the SAR ADC. The large driving current is provided only when the Capacitive Digital-to-Analog Converter (CDAC) is settling. This approach achieves 42% power reduction for the reference voltage buffer, which helps to improve the Figure-of-Merit (FoM) of the total SAR ADC chip. The measurement results show the ADC achieves an SNDR of 35.5 dB at the input frequency of 318.8 MHz. The chip consumes 4.0 mW including the SAR ADC core and the reference voltage buffer, resulting in an FoM of 117.8 fJ/conv.-step.

A reference voltage in capacitor–resister hybrid SAR ADC for front-end readout system of CZT detector**Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (No. 61376034), and the Shaanxi Province Science and Technology Innovation Project (No. 2015KTZDGY03-03).

An on-chip reference voltage has been designed in capacitor–resister hybrid SAR ADC for CZT detector with the TSMC 0.35 μm 2P4M CMOS process. The voltage reference has a dynamic load since using variable capacitors and resistances, which need a large driving ability to deal with the current related to the time and sampling rate. Most of the previous articles about the reference for ADC present only the bandgap part for a low temperature coefficient and high PSRR. However, it is not enough and overall, it needs to consider the output driving ability. The proposed voltage reference is realized by the band-gap reference, voltage generator and output buffer. Apart from a low temperature coefficient and high PSRR, it has the features of a large driving ability and low power consumption. What is more, for CZT detectors application in space, a radiation-hardened design has been considered. The measurement results show that the output reference voltage of the buffer is 4.096 V. When the temperature varied from 0 to 80 °C, the temperature coefficient is 12.2 ppm/°C. The PSRR was −70 dB @ 100 kHz. The drive current of the reference can reach up to 10 mA. The area of the voltage reference in the SAR ADC chip is only 449 × 614 μm2. The total power consumption is only 1.092 mW.

A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

This paper presents the design of a 10-bit, 50MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25bits at a supply voltage of 1.2V, typical process corner and sampling frequency of 50MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697μW and achieves an energy efficiency of 25fJ/conversion-step while occupying a core area of 0.055mm2.

A 10-bit dual-plate sampling DAC with capacitor reuse on-chip reference voltage generator

In this work, a 10-bit dual-plate sampling capacitive DAC with a capacitor reuse on-chip reference voltage generator is proposed. Instead of using the conventional two element switched-capacitor circuit that consists of the charge sampling and summing capacitors, the proposed dual-plate sampling scheme performs the identical operation using a single capacitor. As a result, the capacitor area can be significantly reduced compared to conventional capacitive DACs. Furthermore, the capacitor reuse reference voltage generator does not add much area and power overhead, and the reference amplifier offset cancellation alleviates the reference matching requirements. The proposed DAC is implemented using the CMOS 0.35µm technology with core size of 0.11mm2 and power consumption of 0.8mW for conversion rate of 1.75MS/s. The maximum INL and DNL showed 0.89LSB and 0.47LSB, respectively.

An On-Chip Tunable Frequency Generator for Crystal-Less Low-Power WBAN Radio

This brief presents a digitally tunable frequency generator for crystal-less low-power radios in size-constrained wireless-body-area-network applications. A switched-capacitor frequency-to-voltage converter is used to lock a ring oscillator (RO) to an on-chip reference voltage. The proposed frequency lock loop (FLL) significantly reduces the supply and temperature dependences of the RO frequency by 400x and 13x, respectively, to 0.23%/V and 126 ppm/°C compared to a RO without the FLL. The output frequency can be digitally tuned from 325 to 420 MHz with a resolution of 80 ppm to allow channelization or calibration.

An 8b 250MS/s 0.13µm CMOS ADC using variable references for VGA-to-WUXGA scaler chips

This work proposes an 8b 250MS/s 0.13µm CMOS two-step pipeline ADC using variable references for VGA-to-WUXGA scaler chip applications. The input sample-and-hold amplifier employs MOS capacitor-based gate-bootstrapping circuits to keep the on-resistance of sampling switches constant and to sample wide-band wide-range variable inputs with least distortion. The capacitors of the proposed multiplying D/A converter are laid out in a high matching one-dimensional symmetric shape rather than the conventional common-centroid topology to save chip area. The proposed on-chip current and voltage reference circuits generate variable bottom-side reference voltages with a fixed top-side reference using a single external voltage for processing wide-range variable analog inputs. The two-step reference selection scheme reduces considerably power and area in the last-stage 5b flash ADC. The prototype ADC in a 0.13µm CMOS demonstrates measured differential and integral non-linearities within 0.35 and 0.54 LSB, respectively. The ADC shows a maximum SNDR and SFDR of 44.4 and 56.1 dB at 250 MS/s, respectively. The ADC with an active die area of 0.72 mm2 consumes 58.8---62.4 mW depending on input modes at 250 MS/s and 1.2 V.

Rail-to-Rail, Linear Hot-Electron Injection Programming of Floating-Gate Voltage Bias Generators at 13-Bit Resolution

Hot-electron injection is widely used for accurate programming of on-chip floating-gate voltage and current references. The conventional programming approach involves adapting the duration and magnitude of the injection pulses based on a predictive model which is estimated by using measured data. However, varying the pulse-widths or amplitudes introduces nonlinearity in the injection process which complicates the modeling, calibration and programming procedure. In this paper, we propose a linear hot-electron injection technique which significantly simplifies the programming procedure, and can achieve programming accuracy greater than 13-b which is limited by the thermal noise from the injection process. The procedure employs an active feedback circuit which ensures that all the nonlinear factors affecting the hot-electron injection process are held constant, thus achieving a stable and controllable injection rate. Measured results using an array of floating-gate voltage reference prototyped in a 0.5-μm standard CMOS process demonstrate that the injection rates can be controlled from 0.1 to 4.1 V for the programmable voltage range. Using 50-ms injection pulses, we show that the average injection rate can be adapted from 6.9 to 250 μV/cycle.

A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

A 12-bit 30 MSPS pipeline analog-to-digital converter (ADC) implemented in 0.13-μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.

A high precision high PSRR bandgap reference with thermal hysteresis protection

To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits, a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations. In addition, an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed. Based on the CSMC 0.5 μm 20 V BCD process, the designed circuit is implemented; the active die area is 0.17 × 0.20 mm2. Simulation and testing results show that the temperature coefficient is 13.7ppm/K with temperature ranging from −40 to 150 °C, the power supply rejection ratio is −98.2 dB, the line regulation is 0.3 mV/V, and the power consumption is only 0.38 mW. The proposed bandgap voltage reference has good characteristics such as small area, low power consumption, good temperature stability, high power supply rejection ratio, as well as low line regulation. This circuit can effectively prevent thermal oscillation and is suitable for on-chip voltage reference in high precision analog, digital and mixed systems.

Low-Cost Calibration Techniques for Smart Temperature Sensors

Smart temperature sensors generally need to be trimmed to obtain measurement errors below ±2°C. The associated temperature calibration procedure is time consuming and therefore costly. This paper presents two, much faster, voltage calibration techniques. Both make use of the fact that a voltage proportional to absolute temperature (PTAT) can be accurately generated on chip. By measuring this voltage, the sensor's actual temperature can be determined, whereupon the sensor can be trimmed to correct for its dominant source of error: spread in the on-chip voltage reference. The first calibration technique consists of measuring the (small) PTAT voltage directly, while the second, more robust alternative does so indirectly, by using an external reference voltage and the on-chip ADC. Experimental results from a prototype fabricated in 0.7 ?m CMOS technology show that after calibration and trimming, these two techniques result in measurement errors (±3?) of ±0.15°C and ±0.25°C, respectively, in a range from -55°C to 125°C.

Jitter characteristics of an on-chip voltage reference-locked time-to-digital converter

The noise and jitter characteristics of an on-chip voltage reference-locked ring oscillator used in the time-to-digital converter (TDC) of the integrated receiver of a pulsed time-of-flight laser rangefinder are presented. The frequency of the ring oscillator, 683 MHz, was locked to the on-chip voltage reference by means of a frequency-to-voltage converter, resulting in better than 90 ppm/°C stability. The noise and jitter transfer characteristics of the loop were derived, and simulations were performed to see the effects of different noise types (white and 1/f noise) on the cumulative jitter of the locked ring oscillator. Finally, these results were verified by jitter measurements performed using an integrated time-to-digital converter (TDC) fabricated on the same die (0.18 μm CMOS process). The cumulative jitter of the on-chip reference-locked ring oscillator was less than 30 ps (sigma value) over a time range of 70 ns, which made it possible to use this oscillator as the heart of a TDC when aiming at centimetre-level precision (1 cm = 67 ps) in laser ranging.

Microcantilever Array Pressure Measurement System for Biomedical Instrumentation

An analog signal processing integrated circuit for microcantilever array has been designed for pressure measurement in biomedical applications. The chip consists of analog multiplexer, instrumentation amplifier, sample-and-hold circuit, on-chip voltage and current references, successive approximation register analog-to-digital converter (ADC) and digital control unit. Root sum square (RSS) error from the overall pressure measurement system including microcantilever array and the application specific integrated circuit (ASIC) is only ±1.79 KPa within the measurement range of 0-300 KPa. The 8-bit ADC attains 45.4 dB signal-to-noise-and-distortion ratio (SNDR) and 56.4 dB spurious-free dynamic range (SFDR), while operating at 772 KHz. The integrated circuit has been fabricated using 0.35-¿m 2-poly 4-metal CMOS process technology. The chip occupies an area of 1.54 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 17.8 mW of power with a single 3.3 V supply.

An 80-MS/s 14-bit pipelined ADC featuring 83 dB SFDR

An 80-MS/s 14-bit pipelined analog-to-digital converter (ADC) is presented in this paper. After gain error and offset extraction from prototype measurement, the improved circuit achieves spurious free dynamic range (SFDR) of 82.9 dB and signal-to-noise-and-distortion ratio (SINAD) of 64.1 dB for a 30.5 MHz input, maintained within 6 dB performance deterioration up to 170 MHz input. Differential nonlinearity (DNL) is 0.66 LSB and integral nonlinearity (INL) is 2.5 LSB. Low-jitter clock amplifier and buffers with balanced loads are used to reduce the jitter and skew between different stages. An on-chip voltage reference generator is schemed with low impedance to reduce noise and spurs of reference signals. The ADC is fabricated in a 0.18-μm CMOS process with core area of 3.86 mm2, and consumes 518 mW at 1.8 V supply.

On-Chip Voltage Reference-Based Time-to-Digital Converter for Pulsed Time-of-Flight Laser Radar Measurements

A fully integrated time-to-digital converter (TDC) for a pulsed time-of-flight laser rangefinder has been designed and fabricated by a standard 0.18-mum CMOS process. The time-to-digital conversion is realized by counting the full clock cycles of an on-chip ring oscillator between timing signals and by recording the state of its 12 phases at the moment of arrival of the timing signals and their delayed replicas. The frequency of the oscillator is stabilized to an on-chip voltage reference by means of a frequency-to-voltage-converter-based feedback loop. The resolution and single-shot precision (standard deviation) of the TDC are ~ 60 ps and less than ~ 50 ps, respectively, in a range of 80 ns. The worst-case temperature dependence of the TDC is less than 50 ppm/degC in the temperature range of 0 degC to 70 degC, corresponding to 0.6 mm/degC at a distance of 12 m (80 ns). The power consumption of the TDC is less than 18 mW.

A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 .MU.m CMOS A/D Converter for 3G Communication Systems

This work describes a 12-bit 100 MS/s 0.13 μm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 μm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm 2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.

A 10 b 200 MS/s 1.8 mm2 83 mW 0.13 m CMOS ADC Based on Highly Linear Integrated Capacitors

This work proposes a 10b 200MS/s 1.8mm 2 83 mW 0.13 μm CMOS ADC based on highly linear integrated capacitors for high-quality video system applications such as next-generation DTV and radar vision and wireless communication system applications such as WLAN, WiMax, SDR, LMDS, and MMDS simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC optimizes chip area and power dissipation at the target resolution and sampling rate. The proposed ADC employs two versions of the SHA with gate-bootstrapped NMOS switches and conventional CMOS switches to verify and compare the input sampling effectiveness. Both of the two versions of the wide-band low-noise SHA maintain 10b input accuracy at 200 MS/s. The proposed all signal-isolated 3-D completely symmetric capacitor layout reduces the device mismatch of two MDACs by isolating each unit capacitor from all neighboring signal lines with all the employed metal lines and by placing extra internal metal lines with a fixed internal bias voltage between signal lines connecting the bottom plate of each unit capacitor. The low-noise on-chip current and voltage references with internal RC filters can select optional off-chip voltage references. The prototype ADC is implemented in a 0.13μm 1P8M CMOS process. The measured DNL and INL are within 0.24 LSB and 0.35 LSB while the ADC shows a maximum SNDR of 54 dB and 48 dB and a maximum SFDR of 67 dB and 61 dB at 200 MS/s and 250 MS/s, respectively. The ADC with an active die area of 1.8 mm 2 consumes 83 mW at 200 MS/s and at a 1.2 V supply.

A 14 mW 2.5 MS/s 14 bit $\Sigma\Delta$ Modulator Using Split-Path Pseudo-Differential Amplifiers

This paper presents the design and experimental results of a 1.25 MHz signal bandwidth 14 bit CMOS SigmaDelta modulator. With our proposed switched-capacitor split-path pseudo-differential amplifiers, this modulator achieves high power efficiency, high sampling frequency, and small die area. A new signal and reference front-end sampling network eliminates the input common-mode voltage and reduces power consumption and linearity requirement of the opamp. A prototype chip has been designed and fabricated in a 0.25 mum CMOS technology with a core area of 0.27 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Experimental results show that an 84 dB dynamic range is achieved over a 1.25 MHz signal bandwidth when clocked at 125 MHz. The power dissipation is 14 mW at 2.4 V including on-chip voltage reference buffers.

Precision Low Voltage and Current References

With shrinking of technologies and its applications, on-chip precision low voltage and current reference generation for analog and mixed signal circuits are becoming difficult. This paper presents on-chip complementary metal oxide semiconductor low voltage and current reference circuits design methodologies for low voltage requirements. The designs are based on the bandgap reference and beta multiplier circuits. These reference circuits are prone to instability and can lock into undesired stable state of operation. To avoid these two conditions one needs to satisfy some conditions. Such issues of these reference circuits for practical implementation are discussed. Circuits like Poweron-reset circuit and startup circuits are used to avoid these state of operations. The peculiarity of theses circuits are that they can be tuned to the specific low voltage and low power requirements.