On-chip Voltage-controlled Oscillator Research Articles

On-Chip Voltage-Controlled Oscillator Based on a Center-Tapped Switched Inductor Using GaN-on-SiC HEMT Technology

This study presents a voltage-controlled oscillator (VCO) in a cross-coupled pair configuration using a multi-tapped switched inductor with two switch-loaded transformers in 0.5 µm GaN technology. Two switch-loaded transformers are placed at the inner and outer portions of the multi-tapped inductor. All the switches are turned off to obtain the lowest sub-band. The outer transformer with three pairs of switches is turned on alternately to provide three sub-band modes. A pair of switches at the inner transformer provide a high-frequency band. Two switch-loaded transformers are turned on to provide the highest sub-band. Six modes are selected to provide a wide tuning range. The frequency tuning range (FTR) of the VCO is 27.8% from 3.81 GHz to 8.04 GHz with a varactor voltage from 13 V to 22 V. At a 1 MHz frequency offset from the carrier frequency of 4.27 GHz, the peak phase noise is −119.17 dBc/Hz. At a power supply of 12 V, the output power of the carrier at 4.27 GHz is 20.9 dBm. The figure of merit is −186.93 dB because the VCO exhibits a high output power, low phase noise, and wide FTR. To the best of the author’s knowledge, the FTR in VCOs made of GaN-based high electron mobility transistors is the widest reported thus far.

An mm-Wave CMOS I–Q Subharmonic Resistive Mixer for Wideband Zero-IF Receivers

In this letter, we propose a novel wideband subharmonically pumped fully differential I–Q resistive mixer architecture, which eliminates the necessity for on-chip dc-blocking capacitors to integrate IF amplifiers. The proposed differential subharmonic mixer topology is verified by presenting a CMOS millimeter-wave monolithic integrated circuit (MMIC), which includes the mixer and two on-chip differential IF amplifiers at the mixer’s I- and Q-channels. The 3-dB IF frequency bandwidth is measured from 0.01 to 5 GHz with a peak conversion gain (CG) of −2 dB and an image rejection ratio (IRR) of more than 25 dB over the IF frequency range. The proposed mixer covers the input signal (RF) frequency from 170 to 185 GHz. The mixer has also been tested with an on-chip voltage-controlled oscillator (VCO) and shows −4.7-dB CG with a 3-dB IF bandwidth from 0.01 to 4.5 GHz.

A 210–284-GHz I–Q Receiver With On-Chip VCO and Divider Chain

A 240-GHz direct conversion I–Q receiver with 74-GHz RF bandwidth is reported. It features a mixer-first architecture with fundamental local oscillator (LO)-frequency Gilbert-cell downconversion mixers, variable-gain baseband amplifiers, and a 240-GHz LO source, making it the first fully integrated 240-GHz I–Q receiver. With a phase noise of −82 dBc/Hz at 1-MHz offset, the LO source has a 27-GHz tuning range and consists of a 120-GHz voltage-controlled oscillator (VCO), a frequency doubler, and a static divide-by-128 chain. The measured peak downconversion gain is 23 dB and is adjustable over 38 dB. Along with the IF bandwidth of 59 GHz, the wide RF bandwidth makes it suitable for both high data-rate communication and emerging quantum computing applications. The chip occupies an area of 1.837 mm2 and consumes 859 mW.

Towards Low-Cost, High-Sensitivity Point-of-Care Diagnostics Using VCO-Based ESR-on-a-Chip Detectors

In this paper, we present a new architecture for a voltage-controlled oscillator (VCO)-based electron spin resonance (ESR) detection for a future use in portable, point-of-care ESR spectrometers. The proposed architecture is centered around an application-specified integrated circuit (ASIC) containing a VCO-based ESR detector with two distinct tuning ports with largely different VCO gains to enable wide frequency sweeps and small-signal frequency modulations while keeping the requirements on the digital-to-analog converter driving the ports manageable. In addition, the proposed ASIC features a second VCO for an on-chip frequency downconversion via mixing. To allow for a precise derivation of the operating frequency from an external reference as it is required for quantitative ESR experiments, the two on-chip VCOs are embedded into an offset phase-locked loop. The proposed architecture is verified with ESR experiments on commonly used ESR standard samples (DPPH and BDPA). In these experiments, a spin sensitivity of $1.7\times 10^{9}~{\text {spins}/(\text {G}\sqrt {\text {Hz}})}$ has been achieved at $B_{0} = {450} {\text {mT}}$ , which is comparable to the state of the art, using a permanent magnet and low-cost signal processing on an field-programmable gate array. The presented proof-of-concept experiments clearly demonstrate the potential of the proposed VCO-based ESR detection system for future point-of-care applications.

A Circuit-Based Approach for Characterizing High Frequency Electromigration Effects

A test chip for studying electromigration (EM) effects under various dc and ac stress conditions was implemented in a 32-nm-high-k metal gate process. The stress current, which can be either dc, pulsed dc, square ac, or real ac, was generated on-chip and applied to 60 devices under test (DUTs) in parallel. An on-chip voltage-controlled oscillator was designed to generate a stress frequency higher 1 GHz while on-chip metal gate heaters were used to raise the DUT temperature to >300 °C for accelerated testing. Both abrupt and progressive failures were observed under dc and pulsed dc stress modes. The abrupt failures could be further divided into two categories based on the final resistance value. Although no ac stress induced failures were observed during our extensive stress experiments, ac stress did have an impact on the subsequent dc EM lifetime. Two possible scenarios are given to explain the high frequency EM results.

DTMOS-Based Pulse Transformer Boost Converter With Complementary Charge Pump for Multisource Energy Harvesting

An energy-harvesting system that accommodates both discrete-time or continuous-time energy sources simultaneously is presented. The core dc–dc converter is a pulse transformer boost converter using dynamic threshold MOS transistor that self-starts at 36 mV-input voltage and generates bipolar output voltages up to ±2.5 V. Employing the dynamic body bias technique to the boost converter power transistor improves power efficiency at sub-300-mV input voltages up to two times over the identical transistor in a conventional configuration. At large harvested power, the source-to-body diode of the power transistor functions as an input voltage limiter. Dynamic threshold MOSFET (DTMOS) also increases transistor saturation current and output power compared to conventional transistors at similar input voltage. Instead of using a linear shunt regulator, excess power is dissipated by internal loss of a bipolar-clocked cross-coupled charge pump. An on-chip voltage-controlled oscillator, which generates clock frequency in proportion to the harvested power, and a unipolar-to-bipolar level shifter are included to drive the charge pump designed. The circuit prototypes are fabricated by using the UMC 0.13- $\mu\mbox{m}$ CMOS process with the triple-well option.

A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback

This paper introduces a continuous-time low-pass sigma-delta modulator operating with a seven-phase 400 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,$</tex> </formula> MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and main digital-to-analog converter (DAC). An on-chip voltage-controlled oscillator and a complementary injection-locked frequency divider are utilized for low-jitter clock signal generation with multiple phases, allowing 3-bit pulse-width modulated feedback with a single-element DAC to avoid performance degradation from unit element mismatch problems associated with conventional multi-bit DACs.

A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks

A fully CMOS integrated RF transceiver for ubiquitous sensor networks in sub-gigahertz industrial, scientific, and medical (ISM)-band applications is implemented and measured. The integrated circuit is fabricated in 0.18-mum CMOS technology and packaged in leadless plastic chip carrier (LPCC) package. The fully monolithic transceiver consists of a receiver, a transmitter, and an RF synthesizer with on-chip voltage-controlled oscillator. The chip fully complies with the IEEE 802.15.4 wireless personal area network in sub-gigahertz mode. The cascaded noise figure of the overall receiver is 9.5 dB and the overall transmitter achieves less than 6.3% error vector magnitude for 40 kb/s mode. The chip uses 1.8-V power supply and the power consumption is 25 mW for reception mode and 29 mW for transmission mode

VCO Design With On-Chip Calibration System

This paper presents a low-supply voltage integrated CMOS voltage-controlled oscillator (VCO) with an on-chip digital VCO calibration control system. The VCO utilizes various state-of-the-art design methods to achieve low phase noise. The calibration system includes a novel high-speed digital divide by two circuit and a counter running on 1-GHz input to enable on-chip frequency measurement. An arithmetic unit and algorithms to perform the calibration are implemented using on-chip logic. Two different types of calibration methods have been implemented and measured in order to compare the proposed VCO gain optimization method with more conventional type of VCO calibration. The measurements show that the VCO design has phase noise from -120.5 dBc/Hz to -118.7 dBc/Hz @ 400-kHz offset, measured over the frequency range from 1.67 to 1.93 GHz. The proposed VCO gain optimization method is capable of reducing the KVCO peak-to-peak variation of the presented VCO design from 54.4% to 29.8% in DCS1800 and PCS1900 GSM transmission bands when compared to the conventional type of calibration method

A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35μm CMOS

A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-/spl mu/m CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13-MHz offset is -77 dBc.

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.

A 2-V low-power CMOS direct-conversion quadrature modulator with integrated quadrature voltage-controlled oscillator and RF amplifier for GHz RF transmitter applications

A compact low-voltage low-power CMOS direct-conversion quadrature modulator with integrated quadrature voltage-controlled oscillator (VCO) and radio frequency (RF) amplifier for wireless transmitter applications is proposed and analyzed. By applying both baseband input signals with quadrature phases and quadrature local oscillator (LO) signals to a set of combiners, the quadrature modulation functions can be implemented. The low-power operation is enabled by the current reuse technique used among quadrature modulator, quadrature VCO, and RF amplifier. Because only two transistors and one resistor are cascoded in the critical path of the proposed quadrature modulator between power supply and ground, the supply voltage can be as low as 1.5 V. The proposed circuit structure is used to design a quadrature modulator chip for 1.9-GHz digital enhanced cordless telecommunications (DECT) transmitter applications. The experimental chip is fabricated by using 0.35-/spl mu/m n-well double-poly-triple-metal (DPTM) CMOS technology. The power dissipation is only 18 mW under 2-V power supply voltage. The on-chip quadrature VCO can provide highly accurate quadrature signals without any phase tuning or trimming.

Fully integrated W-CDMA IF receiver and IF transmitter including IF synthesizer and on-chip VCO for UMTS mobiles

A fully integrated, dual intermediate frequency (IF) receiver and an IF transmitter, each with on-chip IF synthesizer, for use in third-generation wide-band code division multiple access (W-CDMA) mobiles has been implemented in a standard, high-frequency, Si-bipolar process with an f/sub T/ of 25 GHz. The IF receiver (318 MHz) and IF transmitter (285 MHz) include a complete phase-locked loop (PLL) and on-chip voltage-controlled oscillator (VCO) with integrated varactors and transformers. The VCOs are used for on-chip local oscillator (LO) generation and operate at four times IF, 1272 MHz and 1140 MHz, for Rx and Tx, respectively. Fully integrated, active, analog base-band filters further increase functionality and integration level. In the receiver, a channel select filter, composed of a fifth-order Chebyshev lowpass filter and a first-order all-pass filter, is implemented. In the transmitter, a fifth-order Butterworth low-pass filter functions as a reconstruction filter. Both devices operate on 2.7-3.3-V supply. The designs comply with ARIB W-CDMA and UMTS standards. Each chip is mounted in a small outline, 32-pin, leadless surface mount package.

5-GHz SiGe HBT monolithic radio transceiver with tunable filtering

A wide-band CDMA-compliant fully integrated 5-GHz radio transceiver was realized in SiGe heterojunction-bipolar-transistor technology with on-chip tunable voltage controlled oscillator (VCO) tracking filters. It allows for wide-band modulation schemes with bandwidth up to 20 MHz. The receiver has a single-ended single-sideband noise figure of 5.9 dB, more than 40 dB on-chip image rejection, an input compression point of -22 dBm, and larger than 70 dB local-oscillator-RF isolation. The phase noise of the on-chip VCO is -100 and -128 dBc/Hz at 100 kHz and 5 MHz offset from the carrier, respectively. The transmitter output compression point is +10 dBm. An image rejection better than 40 dB throughout the VCO tracking range has been demonstrated in the transmitter with all spurious signals 40 dB below the carrier. The differential transceiver draws 125 mA in transmit mode and 45 mA in receive mode from a 3.5-V supply.

Clock jitter and quantizer metastability in continuous-time delta-sigma modulators

The performance of continuous-time (CT) delta-sigma modulators (/spl Delta//spl Sigma/M's) suffers more severely from time jitter in the quantizer clock than discrete-time designs. Clock jitter adds a random phase modulation to the modulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly uniform sampling clock, a similar whitening can be caused by metastability in the quantizer: a real quantizer has finite regeneration gain, and thus, quantizer inputs near zero take longer to resolve. This paper quantifies the performance lost due to clock jitter in a practical integrated CT /spl Delta//spl Sigma/M clocked with an on-chip voltage-controlled oscillator. It also characterizes metastability in a practical integrated quantizer using the quantizer output zero-crossing time and rise time as a function of both quantizer input voltage and the slope of the input voltage at the sampling instant, and predicts the maximum-achievable performance of a practical CT /spl Delta//spl Sigma/M given jitter and metastability constraints.

A 2 GHz Phase-Locked Loop Frequency Synthesizer with On-Chip VCO

This paper discusses the implementation of the building blocks for a 2 GHz phase-locked loop frequency synthesizer in a standard 0.5 μm BiCMOS process. These blocks include a low-power optimized dual modulus prescaler which is able to operate with input frequencies up to 2.7 GHz, a phase detector with extremely constant gain throughout the input phase difference range, a chargepump with a rail-to-rail output, and an on-chip voltage-controlled oscillator.

A 1.5 Gb/s link interface chipset for computer data transmission

The authors designed a set of four ICs to provide encoding, multiplexing, clock extraction/demultiplexing, and decoding for gigabit-rate serial data transmission. These chips form a high bandwidth data link for point-to-point communication. A new line code is implemented that provides DC balance, efficient encoding, framing, and simple clock extraction. Embedded in the code is a fixed transition used by the phase/frequency locked loop (PLL) for simple clock extraction and frame synchronization. Unlike other links, this PLL requires no trimming for data retiming, either in production or later. An on-chip voltage-controlled oscillator (VCO) with a tuning range of 1.1-1.6 GHz is available for use with the PLL. With this chip set the authors demonstrated a transmission rate of 16 bits in parallel at 75 MHz or, with encoding overhead, a serial rate of 1.5 Gb/s.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Synchronous data recovery in RF communication channels

Synchronous data recovery schemes over narrowband radio-frequency (RF) data channels based on phase-shift keying and frequency-shift keying are described. Experimental systems were breadboarded with 50-MHz analog RF circuits fabricated using a 2-/spl mu/m gate double-poly CMOS technology. Most circuits are developed for quadrature RF data transceiver applications in the 50-MHz commercial RF band, and an experimental frequency-aided Costas loop exhibits a 1-mV input sensitivity with an on-chip voltage-controlled oscillator. Developed circuits are applicable to general phase-locked-loop systems for data and clock recovery in VLSI chips. The 50-MHz quadrature RF section occupies 0.55 mm/SUP 2/ and consumes 150 mW with a 5-V supply.