On-chip VCO Research Articles

An impulse radio duty-cycled radar with ultra-wideband VCO using frequency hopping technique

This paper presents a pulse-based radar with ultra-wideband voltage controlled oscillator for vital-sign application. A series of digital-assisted duty-cycled probing pulses with frequency hopping technique is proposed to mitigate unwanted narrowband interferences, thereby increasing overall system signal-to-noise ratio and then enabling high resolution detection. The RF generator is utilized by an on-chip VCO with the characteristic of wide-band response by digitally switching loaded capacitor array for frequency hopping. The conventional ultra-wideband channel is further divided into several sub-channels for vital-sign sensing. An impulse radio Doppler radar is implemented and integrated with the digital-assisted oscillator to detect physiological information.

A 30/35 GHz Dual-Band Transmitter for Phased Arrays in Communication/Radar Applications

A fully integrated single-channel transmitter is proposed for 30/35 GHz dual-band operation for communication/radar phased array systems. Implemented in a 0.25 µm BiCMOS technology, the transmitter achieves 10° phase shift resolution and 5 bit amplitude resolution suitable for advanced beamforming algorithms for suppression and nulling of side lobes. The integration covers from the baseband I/Q modulation to the RF output, including a low phase noise on-chip VCO and dual-band LO generation circuitry. An RF output power of > +14.5 dBm is achieved in both frequency bands by a linear power amplifier. The core circuit occupies a die area of 1.1 mm 2 and consumes 222–241 mA current from a 3.3 V supply.

A low-power wideband multi-frequency synthesizer for mobile TV tuner ICs

A low-power wideband frequency synthesizer that generates multiple LO frequencies for mobile TV tuner ICs is presented. The synthesizer utilizes a single on-chip LC VCO and an odd-order frequency division technique to achieve both low power and small silicon area. The integrated LC VCO has a tuning range of 2.3 to 3.85GHz. With a division ratio of 2, 4, 6, 12, 16, 24, and 32, the LO generation block supports FM, VHF III, UHF, Europe-L, and USA-L bands. The measured LO phase noise for the L-band is under -79dBc/Hz at an offset of 10kHz. The synthesizer implemented in 0.18-µ m CMOS technology occupies an area of about 1.2mm2and dissipates up to 33.5mW from a 1.8-V supply.

A crystal-tolerant fully integrated CMOS low-IF dual-band GPS receiver

This paper presents the design of a dual-band L1/L2 GPS receiver, that can be easily integrated in portable devices (mainly GSM mobile phones). For the ease of integration with GSM wireless systems the receiver can tolerate most of the common GSM crystals, besides the GPS crystals, this will eliminate the need to use another crystal on board. A new frequency plan is presented to satisfy this requirement. A low-IF receiver architecture is used for dual-band operation with analog on-chip image rejection. The receiver is composed of a narrow-band LNA for each band, dual down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and a fully integrated frequency synthesizer including an on-chip VCO and loop filter. The complex filter can accept IF frequency variation of 10% around 4.092 MHz which allows the use of the commonly used 10/13/26 MHz GSM crystals and all the GPS crystals. The synthesizer generates the LO signals for both L1/L2 bands with an average phase noise of ?95 dBc/Hz. The receiver exhibits maximum gain of 112 and 115 dB, noise figures of 4 and 3.6 dB, and input compression points of ?76 and ?79 dBm for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection greater than 25 dB and gain control range over 80 dB. The receiver is designed in 0.13 μm CMOS technology and consumes 18 mW from a 1.2-V supply.

A Broadband Double-Conversion RF Tuner

A prototype design of upconverter and downconverter units for a double-conversion cable-modem RF tuner are presented. The upconverter upconverts a channel from 47--862 MHz input band to around 1575 MHz intermediate frequency. The image-reject downconverter shifts the channel to 36.125 MHz (EU) or to 43.75 MHz (US). The upconverter includes a variable-gain low-noise amplifier, a double-balanced mixer, a three-stage VCO bank for LO generation and a divide-by-two circuit for driving an external PLL. The downconverter includes a LNA, image-reject mixers in Hartley configuration, a 3-stage polyphase filter, an IF-amplifier and a SAW driver. For the second LO generation the circuit includes a 6-GHz on-chip VCO, a divide-by-four circuit for quadrature LO and a divide-by-16 for feeding an external PLL. Signal reversal switching in the LO buffer can be used for the selection of LSB/USB injection. All building blocks are presented in this paper and experimental results are given from the upconverter, downconverter, and RF tuner demonstrator including SAW filters with center frequencies at 1575 and 44 MHz. The circuits are fabricated in a 0.9-? m SiGe bipolar process.

A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop

A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-/spl mu/m CMOS technology is developed for the wireless integrated network sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain (K/sub VCO/) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in order to improve the reference spurs and noise performance. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset frequency and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3-V supply.

A 2 GHz Phase-Locked Loop Frequency Synthesizer with On-Chip VCO

This paper discusses the implementation of the building blocks for a 2 GHz phase-locked loop frequency synthesizer in a standard 0.5 μm BiCMOS process. These blocks include a low-power optimized dual modulus prescaler which is able to operate with input frequencies up to 2.7 GHz, a phase detector with extremely constant gain throughout the input phase difference range, a chargepump with a rail-to-rail output, and an on-chip voltage-controlled oscillator.

A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling

A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-/spl mu/m HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This parallelism is achieved by using multiple phases tapped from a PLL using the phase spacing to determine the bit time. Using an 8:1 multiplexer yields 4 Gbits/s, with an on-chip VCO running at 500 MHz. The internal logic runs at 250 MHz. For robust data recovery, the input is sampled at 3/spl times/ the bit rate and uses a digital phase-picking logic to recover the data. The digital phase picking can adjust the sample at the clock rate to allow high tracking bandwidth. With a 3.3-V supply, the chip has a measured bit error rate (BER) of <10/sup -14/.

A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications

A monolithic 1.9-GHz, 198-mW, 0.6-/spl mu/m CMOS receiver which meets the specifications of the Digital Enhanced Cordless Telecommunications (DECT) standard is described. All of the RF, IF, and baseband receiver components, with the exception of the frequency synthesizers, have been integrated into a single chip solution. A description is given of a wide-band IF with double conversion architecture which eliminates the need for the discrete-component noise and IF filters in addition to facilitating the eventual integration of the frequency synthesizer blocks with on-chip VCO's. The prototype device utilizes a 3.3-V supply and includes a low noise amplifier, an image-rejection mixer, and two quadrature baseband signal paths each of which includes a second-order Sallen and Key anti-alias filter, an eighth-order switched-capacitor filter network followed by a 10-b pipelined analog-to-digital converter (ADC). The experimental device has a measured receiver reference sensitivity of -90 dBm, an input referred IP3 of -7 dBm, a P/sub -1 dB/ of -24 dBm, and an image-rejection ratio of -55 dBc across the DECT bands.

A two-chip 1.5-GBd serial link interface

A silicon bipolar transmitter and receiver chip pair transfers parallel data across a 1.5-GBd serial link. A new 'conditional-invert master transition' code and phase-locked loop that provide adjustment-free clock recovery and frame synchronization are described and analyzed. The packaged parts require no external components and operate over a range of 700 to 1500 MHz using an on-chip VCO. The line code and handshake protocol have been accepted by the serial-HIPPI implementor's group for serially transmitting 800-Mb/s HIPPI data, an ANSI standard, and by SCI-FI, an IEEE standard for interconnecting cooperating computers. >