On-chip Ring Oscillator Research Articles

A Multilabel Active Learning Framework for Microcontroller Performance Screening

In safety-critical applications, microcontrollers have to be tested to satisfy strict quality and performances constraints. It has been demonstrated that on-chip ring oscillators can be used as speed monitors to reliably predict the performances. However, any machine-learning model is likely to be inaccurate if trained on an inadequate dataset, and labeling data for training is quite a costly process. In this paper, we present a methodology based on active learning to select the best samples to be included in the training set, significantly reducing the time and cost required. Moreover, since different speed measurements are available, we designed a multi-label technique to take advantage of their correlations. Experimental results demonstrate that the approach halves the training-set size, with respect to a random-labelling, while it increases the predictive accuracy, with respect to standard single-label machine-learning models.

A Novel Authentication Methodology to Detect Counterfeit PCB Using PCB Trace-Based Ring Oscillator

The existence of counterfeit products, e.g., integrated circuits (ICs) and printed circuit boards (PCBs), in the modern semiconductor supply chain has seriously jeopardized the security and reliability of electronic systems, and has also caused the loss of suppliers’ profit and reputation. Most of existing research papers prevent or detect counterfeit IC and PCB substrate separately, without testing the PCB as a whole, and often require the assistance of external equipment. In this article, a novel ring oscillator-based PCB authentication (ROPA) methodology to detect counterfeit PCB through supply chain is proposed, which utilizes PCB trace-based ring oscillators (PTRO) assisted by on-chip ring oscillators, and a novel PCB signature extraction methodology. By switching the PCB to different load modes, the signature can reflect the process variations in PCB traces and overall impedance. The ROPA can provide both IC and PCB authentication independently of external equipments, and allows remote authentication for the user. The ROPA structure has shown advantageous area (0.301% on average) and power (0.355% on average) overhead when implemented on a number of benchmarks. Then the ROPA is implemented on a set of authentic and counterfeit FPGA development boards to verify the effectiveness on counterfeit detection. The results show that the proposed method provides 96.7% confidence in detecting tampered PCBs and 100% confidence in detecting overproduced, recycled, and cloned PCBs.

Rail-to-Rail Timing Signals Generation Using InGaZnO TFTs For Flexible X-Ray Detector

This paper reports on-chip rail-to-rail timing signals generation thin-film circuits for the first time. These circuits, based on a-IGZO thin-film transistors (TFTs) with a simple staggered bottom gate structure, allow row and column selection of a sensor matrix embedded in a flexible radiation sensing system. They include on-chip clock generator (ring oscillator), column selector (shift register) and row-selector (a frequency divider and a shift register). They are realised with rail-to-rail logic gates with level-shifting ability that can perform inversion and NAND logic operations. These logic gates are capable of providing full output swing between supply rails, V DD and V SS , by introducing a single additional switch for each input in bootstrapping logic gates. These circuits were characterised under normal ambient atmosphere and show an improved performance compared to the conventional logic gates with diode connected load and pseudo CMOS counterparts. By using these high-performance logic gates, a complete rail-to-rail frequency divider is presented from measurements using D-Flip Flop. In order to realize a complete compact system, an on-chip ring oscillator (output clock frequency around 1 kHz) and a shift register are also presented from simulations, where these circuits show a power consumption of 1.5 mW and 0.82 mW at a supply voltage of 8 V, respectively. While the circuit concepts described here were designed for an X-ray sensing system, they can be readily expanded to other domains where flexible on-chip timing signal generation is required, such as, smart packaging, biomedical wearable devices and RFIDs.

Highly Integrated 3 V Supply Electronics for Electromagnetic Energy Harvesters With Minimum 0.4 V $_{\mathbf{peak}}$ Input

This paper presents a self-powered interface enabling battery-like operation with a regulated 3 V output from ac signals as low as 0.4 Vpeak, generated by electromagnetic energy harvesters under low frequency vibrations. As the first stage of the 180 nm standard CMOS circuit, harvested signal is rectified through an ac/dc doubler with active diodes powered internally by a passive ac/dc quadrupler. The voltage is boosted in the second stage through a low voltage charge pump stimulated by an on-chip ring oscillator. The output is finally regulated to 3 V at the last stage. The voltage doubling rectification stage deviates by less than 40 mV from ideal expectation for the validated 0.15–1 V input voltage range. The full system delivers 3 V output to 4.4 MΩ load for input voltage of 0.4 V peak, which is the lowest operable input voltage in the literature. The demonstrated system generates 9 μ W of dc power with 3 V stable output for 32 μ W input, whereas the circuit is able to supply even more output power for higher input power levels. The maximum efficiency of the rectification stage is 86%, while the full system efficiency is 37% and 28% for unregulated and regulated operation, respectively, when interfaced to an in-house electromagnetic energy harvester under 8 Hz 0.1 g vibration.

A Fully Integrated and Battery-Free Interface for Low-Voltage Electromagnetic Energy Harvesters

This paper presents a fully integrated and battery-free 90 nm interface circuit for ac/dc conversion and step up of low-voltage ac signals generated by electromagnetic (EM) energy harvesters. The circuit is composed of two stages: The rectifier in the first stage utilizes an improved ac/dc doubler structure with active diodes internally powered by a passive ac/dc doubler and custom-designed comparators to minimize the voltage drops. With this, the efficiency is enhanced to 67% while providing 0.61 V to 40 μA load. The second stage is a dc/dc converter utilizing a low-voltage charge pump with an on-chip ring oscillator for further voltage step up. The rectifier stage is functional down to 125 mV input peak voltage, and the full interface circuit can maintain more than 1 V dc at 1 MΩ load for input peak voltages higher than 0.4 V. The circuit delivers 2.48 V to a 4.4 MΩ load, when interfaced to an in-house EM harvester, operating under 10 Hz, 0.5 g vibration.

Detection of trojans using a combined ring oscillator network and off-chip transient power analysis

Verifying the trustworthiness of Integrated Circuits (ICs) is of utmost importance, as hardware Trojans may destroy ICs bound for critical applications. A novel methodology combining on-chip structure with external current measurements is proposed to verify whether or not an IC is Trojan free. This method considers Trojans' impact on neighboring cells and on the entire IC's power consumption, and effectively localizes the measurement of dynamic power. To achieve this, we develop a new on-chip ring oscillator network structure distributed across the entire chip and place each ring oscillator's components in different rows of a standard-cell design. By developing novel statistical data analysis, the effect of process variations on the ICs' transient power will be separated from the effect of Trojans. Simulation results using 90nm technology and experimental results on Xilinx Spartan-6 FPGAs demonstrate the efficiency of our proposed method.

Interface Trap Characterization of a 5.8-$\hbox{\rm{ \AA}}$ EOT p-MOSFET Using High-Frequency On-Chip Ring Oscillator Charge Pumping Technique

Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.

Jitter characteristics of an on-chip voltage reference-locked time-to-digital converter

The noise and jitter characteristics of an on-chip voltage reference-locked ring oscillator used in the time-to-digital converter (TDC) of the integrated receiver of a pulsed time-of-flight laser rangefinder are presented. The frequency of the ring oscillator, 683 MHz, was locked to the on-chip voltage reference by means of a frequency-to-voltage converter, resulting in better than 90 ppm/°C stability. The noise and jitter transfer characteristics of the loop were derived, and simulations were performed to see the effects of different noise types (white and 1/f noise) on the cumulative jitter of the locked ring oscillator. Finally, these results were verified by jitter measurements performed using an integrated time-to-digital converter (TDC) fabricated on the same die (0.18 μm CMOS process). The cumulative jitter of the on-chip reference-locked ring oscillator was less than 30 ps (sigma value) over a time range of 70 ns, which made it possible to use this oscillator as the heart of a TDC when aiming at centimetre-level precision (1 cm = 67 ps) in laser ranging.

An All-Digital Self-Calibration Method for a Vernier-Based Time-to-Digital Converter

This paper presents a new calibration method for a Vernier-based time-to-digital converter (TDC). In the proposed method, delay lines in the TDC are configured as on-chip ring oscillators for generating a sequence of time events. These time events are applied to the TDC in the calibration mode, and then, the probability distribution of output codes is determined. The variations of the quantization step and the actual transfer characteristic representing the TDC are estimated through statistical analysis of the output codes. The proposed method eliminates the need for accurate external sources typically used for TDC calibration. Simulation and experimental results using a field-programmable gate array platform indicate that the method can successfully be employed to calibrate high-resolution TDCs with reasonable accuracy.

On-Chip Voltage Reference-Based Time-to-Digital Converter for Pulsed Time-of-Flight Laser Radar Measurements

A fully integrated time-to-digital converter (TDC) for a pulsed time-of-flight laser rangefinder has been designed and fabricated by a standard 0.18-mum CMOS process. The time-to-digital conversion is realized by counting the full clock cycles of an on-chip ring oscillator between timing signals and by recording the state of its 12 phases at the moment of arrival of the timing signals and their delayed replicas. The frequency of the oscillator is stabilized to an on-chip voltage reference by means of a frequency-to-voltage-converter-based feedback loop. The resolution and single-shot precision (standard deviation) of the TDC are ~ 60 ps and less than ~ 50 ps, respectively, in a range of 80 ns. The worst-case temperature dependence of the TDC is less than 50 ppm/degC in the temperature range of 0 degC to 70 degC, corresponding to 0.6 mm/degC at a distance of 12 m (80 ns). The power consumption of the TDC is less than 18 mW.

A 2.4-GHz Ring-Oscillator-Based CMOS Frequency Synthesizer With a Fractional Divider Dual-PLL Architecture

A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the second-stage wide-band PLL suppresses VCO phase noise so that simultaneous suppression of phase noise and spur is achieved. A new low-power, low-noise, low-frequency ring oscillator is designed for this narrow-band PLL. The chip was designed in 0.35-/spl mu/m CMOS technology and achieves a phase noise of -97 dBc/Hz at 1-MHz offset and spurs of -55 dBc. The chip's output frequency varies from 2.4 to 2.5 GHz; the chip consumes 15 mA from a 3.3-V supply and occupies 3.7 mm/spl deg/.

Movable micromachined silicon plates with integrated position sensing

A process for fabricating large silicon plates of varying thicknesses suspended by thin, flexible polyimide beams has been developed.The plates have been integrated with an on-chip ring oscillator which provides a read-out of the plate position. The silicon plates can be moved electrostatically and the position of the plate determined by the frequency shift of the ring oscillator. Initial testing of the device yields a full-scale frequency modulation of approximately 2%, corresponding to a full-scale frequency shift of 13 kHz from a zero-deflection frequency of 680 kHz.