On-chip Power Amplifier Research Articles

A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration

A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency tripler provides 10.6 dB better 300 MHz spur reduction compared to that of the conventional frequency tripler by adding a series high-pass filter. The two-phase 20% duty-cycle and single-ended 50% duty-cycle calibration circuits drive the frequency tripler and Class-D PA, respectively, suppressing unwanted spurs significantly. The digital duty-cycle/phase calibration circuits, designed based on the quantitative analysis of the stability, offer advantage of technology scaling. The reduced spur relaxes the harmonic filtering requirement at the PA output, leading to an on-chip PA MN with low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> . Implemented in 55 nm CMOS, the proposed TX shows the peak output power of 5.2 dBm and efficiency of 30.6% over 902–928 MHz while dissipating 210 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> in the phase-locked loop (PLL) for 0.9 V supply. All spur component levels stay below −41 dBm with the worst harmonic distortion of −48.5 dBc. The proposed TX achieves 100 kbps of data rate for the BFSK modulated signals with the corresponding FSK error of 3.2%.

A Wideband SiGe BiCMOS Frequency Doubler With 6.5-dBm Peak Output Power for Millimeter-Wave Signal Sources

This paper presents a balanced frequency doubler with 6.5-dBm peak output power at 204 GHz in 130-nm SiGe BiCMOS technology ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> = 210/250 GHz). To convert the single-ended input signal to a differential signal for balanced operation, an on-chip transformer-based balun is employed. Detailed design procedure and compensation techniques to lower the imbalance at the output ports, based on mixed mode S parameters are proposed and verified analytically and through electromagnetic simulations. The use of optimized harmonic reflectors at the input port results in a 2-dBm increase in output power without sacrificing the bandwidth of interest. The measured conversion loss of the frequency doubler is 9 dB with 6-dBm input power at 204-GHz output. The measured peak output power is 6.5 dBm with an on-chip power amplifier stage. The 3-dB output power bandwidth is measured to be wider than 50 GHz (170-220 GHz). The total chip area of the doubler is 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the dc power consumption is 90 mW from a 1.8-V supply, which corresponds to a 5% collector efficiency.

Performance Comparison of Flip-Chip-Assembled 5-GHz 0.18-$\mu{\rm m}$ CMOS Power Amplifiers on Different Packaging Substrates

In this paper, three 5-GHz power amplifiers (PAs) are presented, which were implemented in 0.18- μm CMOS technology on different package substrates using flip-chip assembly. To make a fair comparison, the three PAs use the same circuit topology and transistor peripherals. The first case is a fully on-chip integrated CMOS PA with on-chip inductors. The second case uses low-temperature cofired ceramic (LTCC) inductors for the matching network, and the CMOS die is flip-chip-assembled on the LTCC substrate. For the last case, the CMOS bare die is assembled on the ceramic integrated passive device (CIPD) substrate, also by the flip-chip technique, and CIPD inductors are used as the matching network. Moreover, the PA performances with respect to the quality factor of inductors are discussed and verified with the experimental results. The fully on-chip integrated CMOS PA performs at 25.2 dB gain and 22.5 dBm OPSAT with a peak PAE of 22%. The system-in-package (SiP) CMOS PA on LTCC demonstrates 27 dB gain and 23.5 dBm OPSAT with a peak PAE of 27.5%, and the SiP CMOS PA on CIPD performs with 26.8 dB gain and 24 dBm of OPSAT with a peak PAE of 30%. With low-loss inductors on LTCC or CIPD, the maximum improvements of gain and PAE at PSAT can be up to 1.5 dB and 8 percentage Points, compared to the fully on-chip PA. To our knowledge, this is the first comprehensive PA performance comparison for different SiP approaches.

A CMOS WCDMA/WLAN Digital Polar Transmitter With AM Replica Feedback Linearization

This paper presents a 65 nm CMOS digital polar transmitter with on-chip power amplifier (PA) for WCDMA and WLAN application. The proposed architecture is composed of a digital interpolation filter for up-sampling of the input amplitude-control word (ACW), a 9-bit switched-capacitor array for the digital polar modulation (DPM), and a 6-bit PA array to achieve the output power range for the target applications. A linearization technique is implemented by adaptively changing the PA bias voltage according to the RF envelope. To generate this bias voltage, the RF envelope of the PA input is extracted by a digital-to-analog converter (DAC) with the ACW signals as its input. A scaled replica of the PA, which only needs to operate at the Amplitude Modulation (AM) frequency, is employed to sense the RF envelope and to regulate the PA bias voltage with an analog feedback loop to minimize the distortion in the AM path. Even without amplitude pre-distortion, the transmitter system measures RMS-EVM of 2.83% and 4.07% for WCDMA and WLAN 54-Mb/s 64-QAM OFDM respectively while providing a peak output power of 20.4 dBm with PAE 32.3%.

Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier

An energy-efficient, 3.5-GHz, direct-conversion RF transmitter with integrated 23-dBm, Class-B power amplifier (PA) is fabricated in a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS process for the reliable transmission of 20-MHz bandwidth OFDM signals. Assisted by an integrated feedback path, a two-dimensional, digital look-up table (2-D LUT) adapted by complex gradient-descent algorithms compensates for the I/Q mismatch and memoryless nonlinearities of the whole transmit path, including the severe amplitude and phase distortions of the on-chip PA. Fifth-order Butterworth transmit filters with 34-MHz cutoff frequency sufficiently attenuate the aliases of the 80-MS/s digital-to-analog converters (DACs), while retaining high in-band fidelity without corrupting the predistorted signal. When a 20-MHz, 64-QAM OFDM signal with 9.6-dB peak-to-average power ratio (PAPR) was transmitted, the measured average drain efficiency (DE) of the PA was 12.5% at 9.6-dB back-off and 17.5% at 7-dB back-off, and the corresponding error-vector magnitude (EVM) was measured to be <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 29.6 dB and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 26.3 dB with equalization, respectively. A peak DE of 55% and a 25-dBm saturated output power were also measured for the same PA in a stand-alone package.