Optical Network-on-chip Research Articles

Fuzzy logic-based routing and wavelength assignment with traffic prediction for optical network-on-chip

In Optical Network-on-Chip (ONoC), both routing and wavelength assignment (RWA) have an impact on the Optical Signal-to-Noise Ratio (OSNR), which further influence the power efficiency and scalability. In the state-of-the-art, the consideration of routing is separate with the wavelength assignment, which could not reach a holistic optimization. Also, there is a need of trade-off among multidimensional performance factors in the design of RWA. In this article, we propose a Multidimensional Integrated Predictive RWA (named as MIP-RWA), based on the Fuzzy Logic System (FLS). The MIP-RWA considers routing and wavelength assignment holistically, taking into consideration of multidimensional performance factors at the same time. The predictive scheme is proposed to work with RWA and further reduce the delay in RWA. The evaluation shows that the proposed MIP-RWA can obtain better trade-off of the performance factors. The traffic prediction accuracy of the Fuzzy Neural Network (FNN) improves by 5.29%, 4.79%, and 6.2% respectively under the uniform, transpose, and hotspot traffic, compared with the Long Short-Term Memory (LSTM)-based. Thanks to the traffic predictive scheme, the proposed MIP-RWA reduces the end-to-end delay (ete delay) by 17.77%, 17.39%, and 16.66% respectively under uniform, transpose, and hotspot traffic, compared with the methods without predictive scheme. Also, compared with current RWA methods, the proposed MIP-RWA improves 11.21 dB in OSNR and 21.47% in delay in average.

On-chip photoelectric hybrid convolutional accelerator based on Bragg grating array

We propose an on-chip photoelectric hybrid convolution accelerator based on Bragg grating array. The weight of the convolution kernel can be adjusted by controlling the central wavelengths of the Bragg grating array. We conducted simulation verification of the functionality and scalability of this on-chip photoelectric hybrid convolution accelerator. Subsequently, we constructed a neural network model to conduct handwritten digit classification simulations using this accelerator, achieving a simulation accuracy of 93.99%. Finally, the concept of the proposed on-chip photoelectric hybrid convolution accelerator is successfully verified. Due to the merits of Bragg grating, the proposed scheme paves the way for realizing high-performance on-chip optical neural networks.

Reinforcement Learning (RL)-Based Holistic Routing and Wavelength Assignment in Optical Network-on-Chip (ONoC): Distributed or Centralized?

Reinforcement Learning (RL)-Based Holistic Routing and Wavelength Assignment in Optical Network-on-Chip (ONoC): Distributed or Centralized?

Neural-network-based hardware trojan attack prediction and security defense mechanism in optical networks-on-chip

Optical networks-on-chip (ONoCs) have emerged as a compelling platform for many-core systems owing to their notable attributes, including high bandwidth, low latency, and energy efficiency. Nonetheless, the integration of microring resonators (MRs) in ONoCs exposes them to vulnerabilities associated with hardware trojans (HTs). In response, we propose an innovative strategy that combines deep-learning-based HT attack prediction with a robust security defense mechanism to fortify the resilience of ONoCs. For HT attack prediction, we employ a multiple-inputs and multiple-outputs long short-term memory neural network model. This model serves to identify susceptible MRs by forecasting alterations in traffic patterns and detecting internal faults within optical routing nodes. On the defensive front, we introduce a fine-grained defense mechanism based on MR faults. This mechanism effectively thwarts HTs during the optical routing process, thereby optimizing node utilization in ONoCs while concurrently upholding security and reliability. Simulation outcomes underscore the efficacy of the proposed HT attack prediction mechanism, demonstrating high accuracy with a loss rate of less than 0.7%. The measured mean absolute error and root mean squared error stand at 0.045 and 0.07, respectively. Furthermore, when compared to conventional coarse-grained node-based defense algorithms, our solution achieves noteworthy reductions of up to 16.2%, 43.72%, and 44.86% in packet loss rate, insertion loss, and crosstalk noise, respectively.

OpSAVE: Eviction Based Scheme for Efficient Optical Network-on-Chip

For on-chip networks, nanophotonics has been considered a strong alternative owing to its high speed (due to low latency) and high bandwidth (due to wavelength division multiplexing). However, the major hurdle in the adoption of nanophotonic-based on-chip networks is their high static power consumption. Various proposals are there in the literature which try to reduce the static power consumption either by modulating the laser or by allowing the on-chip stations to share the photonic channels. In this paper, we propose OpSAVE— an optical NoC that combines the above two strategies to effectively reduce static power consumption. It proposes a superior prediction mechanism based on the eviction details from the private caches. It explains how shared channels can be used to dynamically balance the load and at the same time handle mispredictions. It allows the optical stations to share both the power and the available bandwidth to increase their utilization. Moreover, OpSAVE proposes to use a double pumping strategy to improve the system performance. We compared our scheme with the state-of-the-art proposals in this domain and the results show that our scheme consumes 4.4X less optical power and at the same time improves the performance by nearly 28%. In the evaluation, we have considered the multicore benchmarks from the Splash and Parsec benchmark suites.

Routing and Wavelength Assignment for Multiple Multicasts in Optical Network-on-Chip (ONoC)

Optical Network-on-Chip (ONoC) is an emerging chip-scale optical interconnection technology to realize high-performance and power-efficient inter-core communication for many-core processors. Multicast communication is popularly used in parallel applications on chip. However, existing researches for multicast in ONoC mainly focus on the optimization of one multicast. This limits the practical applications of the research outcomes because we often face the dynamic formation of multiple multicast groups in real network systems. In this paper, we define the problem of routing and wavelength assignment for multiple multicasts in ONoC with the objective of minimizing the number of wavelengths required. To solve the problem, we first formulate it as an integer programming model for general topologies. Then we design routing policies for special instances that optimally use only one wavelength on mesh topology. For general instances, we design a Group-Partitioning Routing algorithm for Multiple Multicasts (GPRMM). GPRMM decouples a group of multicasts into a number of sub-groups, each of which matching one of the special instances. Theoretical results show that the number of wavelengths required by GPRMM is no more than the Destination Density σd, i.e., the maximum number of multicasts with destinations in the same row or column. Moreover, we find the upper bound and the lower bound on the number of wavelengths required for GPRMM. The wavelength requirement is also upper bounded by the network size n for an n×n mesh network. Simulation results show that GPRMM can reduce the number of wavelengths by 26.7% compared with previous methods. GPRMM has the advantages of low routing complexity, low wavelength requirement, low power consumption, and good scalability.

Design of a Passive Silicon-on-Insulator-Based On-Chip Optical Circulating Network Supporting Mode Conversion and High Optical Isolation

Over the past few decades, on-chip photonic integrated circuits based on silicon photonics (SiPh) platforms have gained widespread attention due to the fact that they offer many advantages, such as high bandwidth, low loss, compact size, low power consumption, and high integration with different photonic devices. The demand for high-speed and high-performance SiPh devices is driven by the significant increase in demand for Internet traffic. In photonic integrated circuits, controlling optical signals to make them circulate in a specific direction is a highly researched area of study. However, achieving a purely passive on-chip optical circulating network on a SiPh platform is very challenging. Therefore, we propose and demonstrate, through simulations, an on-chip optical circulator network on a silicon-on-insulator (SOI) platform. The proposed device can also support mode conversion. The proposed on-chip optical circulating network consists of two kinds of tailor-made multi-mode interferometer (MMI) structures and waveguide crossings. Through the optical power division and mode combination capabilities of the MMI, an optical circulating network supporting high optical isolation and mode conversion is achieved. The proposed optical circulating network has a loss of 1.5 dB at each output port, while maintaining a high isolation of 35 dB in the transmission window from 1530 nm to 1570 nm.

Exploration of a neural-network-based joint method of mapping and wavelength assignment in optical network-on-chip

Optical network-on-chip (ONoC) is promising to provide higher bandwidth and lower latency, compared with the traditional electrical interconnects at either chip-scale or wafer-scale. There is research on the impact of mapping or wavelength assignment on reliability in ONoC. However, mapping and wavelength assignment have an interactive influence on each other, pushing a necessity of research on the joint method. In addition, there are various ways to realize the joint method, which have an influence on the reliability and thus the power efficiency. In this paper, we propose a neural-network-based iterative joint method of mapping and wavelength assignment. Compared to the methods without considering the interactive influence, the proposed iterative joint method based on the continuous Hopfield neural network provides a worst-case optical signal-to-noise ratio (OSNRWC) improvement of at least 61% under the considered applications. Compared to the simultaneous joint method and two-step joint method, the proposed iterative joint method obtains an OSNRWC improvement of at least 17.9% and 64.6%, respectively, under the considered applications. Thanks to the improvement of OSNR, the laser power is reduced by 87.9% by using our method of wavelength assignment, compared to the random method of wavelength assignment.

On chip optical neural networks based on MMI microring resonators for image classification

We propose a new on-chip optical neural network (OONN) based on multimode interference-microring resonators (MMI-RRs). The suggested structure eliminates the need for wavelength division multiplexers (WDM) to create an optical neuron on a single chip. New microring resonator structure based on 4×4 MMI coupler with a size of 24µm × 2900 µm is used for the basic elements of the computation matrix, as a result a higher bandwidth and free spectral range (FSR) can be achieved. The Si3N4 platform along with the graphene sheet is designed to modulate the signals and weights of the neural networks at a very high speed. The Si3N4 can provide wide range of operating wavelengths and can work directly with the wavelengths of color images. The structure's benefits include rapid computing speed, little loss, and the ability to handle both positive and negative values. The OONN has been applied to the MNIST dataset with a speed faster than 2.8 to 14x times compared with the conventional GPU methods.

Implementation of energy-efficient convolutional neural networks based on kernel-pruned silicon photonics.

Silicon-based optical neural networks offer the prospect of high-performance computing on integrated photonic circuits. However, the scalability of on-chip optical depth networks is restricted by the limited energy and space resources. Here, we present a silicon-based photonic convolutional neural network (PCNN) combined with the kernel pruning, in which the optical convolutional computing core of PCNN is a tunable micro-ring weight bank. Our numerical simulation demonstrates the effect of weight mapping accuracy on PCNN performance and we find that the performance of PCNN decreases significantly when the weight mapping accuracy is less than 4.3 bits. Additionally, the experimental demonstration shows that the accuracy of the PCNN on the MNIST dataset has a slight loss compared to the original CNN when 93.75 % of the convolutional kernels are pruned. By making use of kernel pruning, the energy saved by a convolutional kernel removal is about 202.3 mW, and the overall energy saved has a linear relationship with the number of kernels removed. The methodology is scalable and provides a feasible solution for implementing faster and more energy-efficient large-scale optical convolutional neural networks on photonic integrated circuits.

C-DONN: compact diffractive optical neural network with deep learning regression.

A new method to improve the integration level of an on-chip diffractive optical neural network (DONN) is proposed based on a standard silicon-on-insulator (SOI) platform. The metaline, which represents a hidden layer in the integrated on-chip DONN, is composed of subwavelength silica slots, providing a large computation capacity. However, the physical propagation process of light in the subwavelength metalinses generally requires an approximate characterization using slot groups and extra length between adjacent layers, which limits further improvements of the integration of on-chip DONN. In this work, a deep mapping regression model (DMRM) is proposed to characterize the process of light propagation in the metalines. This method improves the integration level of on-chip DONN to over 60,000 and elimnates the need for approximate conditions. Based on this theory, a compact-DONN (C-DONN) is exploited and benchmarked on the Iris plants dataset to verify the performance, yielding a testing accuracy of 93.3%. This method provides a potential solution for future large-scale on-chip integration.

Universal wavelength reuse mechanism for optical networks-on-chip based on a cooperative game

Optical networks-on-chip (ONoCs) based on wavelength division multiplexing (WDM) technology have lower end-to-end (ETE) delay, larger bandwidth, and higher throughput than NoCs. However, the utilization and parallelism of individual wavelengths are essential since WDM technology would require more optical devices to be integrated with ONoCs, leading to higher on-chip overhead. In this paper, we propose an optimal model of communication node cooperation based on game theory, in which the loss of the optical signal on the transmission path for a specific optical receiver sensitivity establishes the payoff function of each participant. In this cooperative game model, the communication nodes are regarded as the participants of the cooperative game. By analyzing the principle of optical router port occupation, the coordinate-based coalition assignment algorithm is proposed to implement fast construction of coalitions and reach the Nash equilibrium of the cooperative game. In Nash equilibrium, the utilization and parallelism of individual wavelengths are higher, and the network’s performance is optimized and improved. Cooperative-game-based ONoCs have more significant throughput and lower ETE delay. The optical signal loss and minimum output power of the optical transmitter can be further reduced at a given optical receiver sensitivity. By applying the cooperative game to ONoCs, the network’s optimization effect becomes more evident as the network scale increases and the number of communication nodes grows.

On-Chip E00-E20 Mode Converter Based on Multi-Mode Interferometer.

Mode converters is a key component in mode-division multiplexing (MDM) systems, which plays a key role in signal processing and multi-mode conversion. In this paper, we propose an MMI-based mode converter on 2%-Δ silica PLC platform. The converter transfers E00 mode to E20 mode with high fabrication tolerance and large bandwidth. The experimental results show that the conversion efficiency can exceed -1.741 dB with the wavelength range of 1500 nm to 1600 nm. The measured conversion efficiency of the mode converter can reach -0.614 dB at 1550 nm. Moreover, the degradation of conversion efficiency is less than 0.713 dB under the deviation of multimode waveguide length and phase shifter width at 1550 nm. The proposed broadband mode converter with high fabrication tolerance is promising for on-chip optical network and commercial applications.

Microstructured All-Optical Switching Based on Two-Dimensional Material

Microstructured all-optical switching, possessing the unique function of light controlling light, is an important part of the on-chip ultra-fast optical connectivity network and integrated logic computing chip. Microstructured all-optical switching has attracted extensive research interest, the latest great developments of which have also yielded progress in nanophotonics, nonlinear optics, optical communications, and integrated optics, etc. The emergence of two-dimensional materials with good third-order optical nonlinearity provides an important driving force for the improvement of all-optical switches. This paper reviews the implementation principles, novel configurations, improved performance indexes, and research progress based on different two-dimensional materials for micro/nano all-optical switching. Not only is a systematic discussion of the current state provided, but also, a brief outlook is afforded on the remaining challenges in the pursuit of the application of practical on-chip microstructured all-optical switching that is based on two-dimensional materials.

System-level reliability assessment of optical network on chip

Optical Network on Chip (ONoC) is now considered a promising alternative to traditional electrical interconnects. Meanwhile, several challenges such as temperature and process variations, aging, crosstalk noise, and insertion loss endanger the data transmission reliability of ONoCs. Many investigations have been made to evaluate the effect of these phenomena on ONoC’s reliability. However, system-level reliability assessment of ONoCs based on the failure rate of its essential elements has not been considered by the researchers yet. In this paper, we offer a reliability framework to calculate the reliability of micro-ring resonator, optical path, optical router, and optical topology architecture. Moreover, we developed a system-level simulator called Reliability Assessment of Photonic Network-on-Chips (RAP-NoC) to evaluate the reliability of different 2D and 3D optical routers and network-on-chip architectures in different data traffic patterns. The simulation results depict that Mesh topology improves the reliability parameter by about 5.2% compared to Torus in the same size and traffic patterns. Also, it can be concluded that Crux and DIPU routers are more reliable than the other 2D and 3D state-of-the-art optical routers.

4 × 4 Integrated Switches Based on On-Chip Wireless Connection through Optical Phased Arrays

Optical Wireless Networks on-Chip are an emerging technology recently proposed to improve the interconnection between different processing units in densely integrated computing architectures. In this work, we propose a 4 × 4 optical wireless switch (OWS) based on optical phased arrays (OPAs) for broadband reconfigurable on-chip communication. The OPA and OWS design criteria are reported. Moreover, the performances of the OWS are analyzed and optimized considering the electromagnetic propagation in on-chip multilayer structures, with different thicknesses of the cladding layer. The effect on the OWS behavior of a non-ideal distribution of the power in input to the OPA is also investigated by designing a 1 × 7 beam splitter, based on a single-stage multi-mode interference (MMI) device to be used as a single element of the OWS. Then, the MMI output signals are considered in input to the transmitting OPAs and the OWS performances are evaluated.

Photonic machine learning with on-chip diffractive optics

Machine learning technologies have been extensively applied in high-performance information-processing fields. However, the computation rate of existing hardware is severely circumscribed by conventional Von Neumann architecture. Photonic approaches have demonstrated extraordinary potential for executing deep learning processes that involve complex calculations. In this work, an on-chip diffractive optical neural network (DONN) based on a silicon-on-insulator platform is proposed to perform machine learning tasks with high integration and low power consumption characteristics. To validate the proposed DONN, we fabricated 1-hidden-layer and 3-hidden-layer on-chip DONNs with footprints of 0.15 mm2 and 0.3 mm2 and experimentally verified their performance on the classification task of the Iris plants dataset, yielding accuracies of 86.7% and 90%, respectively. Furthermore, a 3-hidden-layer on-chip DONN is fabricated to classify the Modified National Institute of Standards and Technology handwritten digit images. The proposed passive on-chip DONN provides a potential solution for accelerating future artificial intelligence hardware with enhanced performance.

Accurate Infinite-Order Crosstalk Calculation for Optical Networks-on-Chip

Optical Networks-on-Chip (ONoCs) are becoming more and more appealing due to rising network requirements in integrated circuits. One important aspect in ONoC design is the amount of crosstalk generated by the network because crosstalk and Signal-to-Noise Ratio (SNR) are strong limiting factors to network scale and performance. Calculation of crosstalk is thus essential for effective ONoC design. Motivated by this fact, we developed a new general linear algebra based method to calculate the steady-state of any system obeying a simple set of rules. We prove that ONoCs follow these rules and show how this general method can be applied in the particular case of ONoCs to calculate accurate first-order and infinite-order crosstalk and SNR results for any ONoC network.

On-Chip Optical Switching Network Architecture Based on Hybrid Wavelength and Mode Division Multiplexing

On-Chip Optical Switching Network Architecture Based on Hybrid Wavelength and Mode Division Multiplexing

Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs

Optical network-on-chip (ONoC) is an emerging upgrade for electronic network-on-chip (ENoC). As a kind of ONoC, wavelength-routed ONoC (WRONoC) shows ultrahigh bandwidth and ultralow latency in data communication. Manually designed WRONoC topologies typically reserve all to all links. This causes the waste of resources. Topology customization for each individual communication network can save resources, but requires automation for efficient design. The state-of-the-art design automation method is not efficient and does not support crosstalk analysis and signal-to-noise ratio (SNR) optimization. Moreover, the state of the art does not consider the physical locations of the data sending/receiving ports, causing unavoidable detours and crossings in the physical layout. In this work, we present FAST+: an automatic topology customization and optimization method. Compared with the state of the art, FAST+ operates much more efficiently and proposes a concrete router-level crosstalk-analysis method and a novel SNR optimization algorithm. This work also provides solutions to avoid detours and crossings in the physical layout. When SNR optimization is not enabled, experimental results show that FAST+ runs thousands times faster than the state of the art on average while providing multiple better or equally good topologies regarding resource usage and the worst case insertion loss. When SNR optimization is enabled, FAST+ provides <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.75\times $ </tex-math></inline-formula> better worst case SNR on average after the optimization while not sacrificing resource usage and the worst case insertion loss.