On-chip Memory Blocks Research Articles

Single-event effects induced by medium-energy protons in 28 nm system-on-chip

Single-event effects (SEEs) induced by medium-energy protons in a 28 nm system-on-chip (SoC) were investigated at the China Institute of Atomic Energy. An on-chip memory block was irradiated with 90 MeV and 70 MeV protons, respectively. Single-bit upset and multi-cell upset events were observed, and an uppermost number of nine upset cells were discovered in the 90 MeV proton irradiation test. The results indicate that the SEE sensitivities of the 28 nm SoC to the 90 MeV and 70 MeV protons were similar. Cosmic Ray Effects on Micro-Electronics Monte Carlo simulations were analyzed, and it demonstrates that protons can induce effects in a 28 nm SoC if their energies are greater than 1.4 MeV and that the lowest corresponding linear energy transfer was 0.142 MeV cm2 mg−1. The similarities and discrepancies of the SEEs induced by the 90 MeV and 70 MeV protons were analyzed.

Concurrent fault simulation on message passing multicomputers

Even though hardware accelerators are common in very large scale integration (VLSI) computer-aided design (CAD), fault simulation is a notable exception because of limited availability of memory, the need for dynamic memory management and the complexity of the algorithms themselves. Although simplified fault simulation algorithms that assume a zero delay circuit model can be accelerated, their applicability is limited. Most application specific integrated circuits (ASIC's) designed in industry today have on-chip memory blocks of different dimensions and characteristics, enhancing the complexity of a fault simulator. In this paper, we present a multiple delay algorithm for concurrent fault simulation of logic gates and functional memory blocks. This algorithm has been implemented on the microprogrammable accelerator for rapid simulation (MARS) hardware accelerator system with a 22 MHz clock and a capacity to simulate circuits with millions of devices. Speedup factors of 20 to 30 are easily achieved when compared to software simulators running on comparable hardware platforms and using identical circuit models.

A hardware logic simulation system

Multiple-delay logic simulation algorithms developed for the microprogrammable accelerator for rapid simulations (MARS) hardware simulator are discussed. In particular, timing-analysis algorithms for event cancellations, spike and race analyses, and oscillation detection are described. It is shown how a reconfigurable set of processors, called processing elements (PEs), can be arranged in a pipelined configuration to implement these algorithms. The algorithms operate within the partitioned-memory, message-passing architecture of MARS. Three logic simulators-two multiple delay and one unit delay-have been implemented using slightly different configuration of the available PEs. In these simulators, VLSI chips are modeled at the gate level with accurate rise/fall delays assigned to each logic primitive. On-chip memory blocks are modeled functionally and are integrated into the simulation framework. The MARS hardware simulator has been tested on many VLSI chip designs and has demonstrated a speed improvement of about 50 times that of an Amdahl 5870 system running a production-quality software simulator while retaining the accuracy of simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>