On-chip Interconnect Applications Research Articles

Ultrafast reconfigurable nanoscale optical switch based on photonic crystal waveguide

We propose reconfigurable photonic switches with very low input power, ultracompact size, fast response, and low optical loss for high-speed optical network and on-chip interconnect applications. The photonic crystal waveguide-based nanostructure is used to realize the reconfigurable 3 × 3 and 4 × 4 optical switches. The two different operating wavelengths of 1550 and 1630 nm play a significant role in the nanophotonic switching platform. The reconfiguration of optical signal path is effectively attained using these wavelengths with low delay time and high data rate. The performance of nanoswitch parameters is numerically investigated by the finite-difference time-domain method. The proposed optical switch is designed with a low input power of 0.5 mW, fast response time of 607.33 fs, and high data rate of 1.646 Tbps. This high-performance device can be suitable for lightwave communication network, quantum computing, and nanoscale photonic integrated systems.

Athermal Polysilicon Mach-Zehnder Interferometer in Bulk CMOS

This study demonstrates the first athermal polysilicon Mach-Zehnder interferometer (MZI) based on strip and subwavelength grating waveguides in commercialized bulk CMOS without any process modification. As-fabricated MZI exhibits a temperature sensitivity of ±4 pm/°C over 1500~1600 nm wavelength range with a slope of -0.055 pm/°C/nm. This wavelength filtering device is therefore immune from the temperature gradient issue arising from the nearby electronic circuits, thus is promising for practical on-chip optical interconnect and sensor applications in bulk CMOS.

Performance analysis of carbon nanotubes forfuture highspeed VLSI on-chip interconnect applications

Performance analysis of carbon nanotubes forfuture highspeed VLSI on-chip interconnect applications

Aluminum plasmonic waveguides co-integrated with Si3N4 photonics using CMOS processes

Co-integrating CMOS plasmonics and photonics became the “sweet spot” to hit in order to combine their benefits and allow for volume manufacturing of plasmo-photonic integrated circuits. Plasmonics can naturally interface photonics with electronics while offering strong mode confinement, enabling in this way on-chip data interconnects when tailored to single-mode waveguides, as well as high-sensitivity biosensors when exposing Surface-Plasmon-Polariton (SPP) modes in aqueous environment. Their synergy with low-loss photonics can tolerate the high plasmonic propagation losses in interconnect applications, offering at the same time a powerful portfolio of passive photonic functions towards avoiding the use of bulk optics for SPP excitation and facilitating compact biosensor setups. The co-integration roadmap has to proceed, however, over the utilization of fully CMOS compatible material platforms and manufacturing processes in order to allow for a practical deployment route. Herein, we demonstrate for the first time Aluminum plasmonic waveguides co-integrated with Si3N4 photonics using CMOS manufacturing processes. We validate the data carrying credentials of CMOS plasmonics with 25 Gb/s data traffic and we confirm successful plasmonic propagation in both air and water-cladded waveguide configurations. This platform can potentially fuel the deployment of co-integrated plasmonic and photonic structures using CMOS processes for biosensing and on-chip interconnect applications.

(Invited) Status Review of SSI-LEDs

After several years of confirmation of the light emission phenomena and theory development, the author’s group first reported the solid-state incandescent light emitting device (SSI-LED) in 2013 [1]. The status of this kind of device is reviewed with respect to the structure, composition materials, fabrication process, physics, and reliability. The principle of light emission from the SSI-LED is the thermal excitation of the high-k dielectric surrounded nano-resistors during the passage of a current. Figure 1 shows (a) the cross-sectional view of the structure and (b) a top view of light emitted from a device. These nano-resistors are formed from the hard breakdown of the MOS capacitor. Different from the conventional wisdom that the whole dielectric film would be broken from a single location, the film breaks at a large number of spots evenly distributed across the gate electrode covered area. This phenomenon can be contributed to the good initial gate dielectric thin film, i.e., low leakage current, homogeneous physical and chemical properties, and uniform thickness. SSI-LEDs have also been fabricated from MOS capacitors with various kinds of high-k dielectrics, such as HfOx, Zr-doped HfOx (ZrHfO), WOx, AlOx, TaOx, TiOx, and NiOx. In addition, SSI-LEDs with gate dielectrics composed of the high-k/nanocrystals (nc-Si, -ZnO, -ITO, -CdSe, -MoOx, etc.)/high-k thin film stacks have also been successfully fabricated [2,3]. The emission spectrum of the SSI-LED convers the whole visible and part of the IR wavelength range independent of the original dielectric material or the including of nanocrystals in the dielectric structure. The shape of the emission spectrum is similar to that of the solar light in the visible wavelength. Other light characteristics, such as the CCT, CRI, and chromaticity, are similar to those of the incandescent light. Therefore, light is emitted from the black body radiation following the Planck’s law. The light emission efficiency of a SSI-LED is determined by the efficiency of the thermal excitation of the nano-resistor, which can be estimated from the emission spectrum energy and the input power. Since the range and shape of the emitted light is fixed, the former is dependent on its intensity. In our studies, it was observed that the intensity of the emitted light from a SSI-LED was directly related the current density, which is related to the resistance along the current path. The resistance along the current path is mainly composed of resistances of the nano-resistor, the nano-resistor/Si contact, the Si substrate, and the gate electrode. The first two items are dependent on the material of the original high-k dielectric and the bond structure of the conductive path. The electrical properties of the nano-resistor is between those of a metal and a semiconductor [4]. The SSI-LED made of the nc-CdSe embedded ZrHfO gate dielectric has been operated for a long period, e.g., > 20,000 hours, under atmosphere without failure [5]. The surrounding dielectric film prevents the exposure of the nano-resistor the atmosphere. The failure of the device is gradual, which shows as the decrease of the leakage current and the red shift of the light spectrum with the increase of the time. In summary, the principle of light emission, composition materials, efficiency, and lifetime of the SSI-LED have been examined and discussed. The warm white light emitted from this kind of device can be used in a wide range of lighting, on-chip interconnect, and other applications. The author acknowledge his students, postdoctoral and visiting scholars Chi-Chou Lin, Shumao Zhang, and Xiaoning Zhang for dedicated work in the fabrication and testing of SSI-LEDs. [1] Y. Kuo et al., APL, 102, 031117 (2013). [2] Y. Kuo, IEEE TED, 62, 3536 (2015). [3] C.-C. Lin et al., Appl. Phys. Lett., 106, 121107 (2015). [4] S. Zhang et al., IOP J. Phys. D, accepted (2017). [5] Y. Kuo et al., AVS 63rd Intl. Symp. Abst. #1844 (2016). Figure 1

A Survey of Carbon Nanotube Interconnects for Energy Efficient Integrated Circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design.

Formation of Crystalline Si Optical Waveguides on Bulk (100) Si Substrate as a New Platform for On-Chip Interconnect Applications

Lightwave transmission is a promising candidate for data interconnections, including the short-distance data communication. The method by which photonics and electronics ought to be integrated is developing and not well resolved yet. In particular, the different requirements of buried oxide thickness for photonics and electronics hamper their integration on the same chip. In this paper, we present a crystalline Si-core waveguide as the platform of interconnection and proceed to investigate its characteristics. The Si-core of the waveguide on bulk (100) Si substrate is formed by an excimer laser system through shape reformation. The SiO2 cladding is later on created through oxidation process. Though the Si-core's shape has changed, it still preserves its monocrystalline properties, and displays a broadband transmission. This test shows several local defects along axial direction cause obvious scattering of the guided wave, and propagation loss is estimated to be about 7 dB/cm. We think the defects come from an observed wavy structure and this loss is improvable via our proposed methods. In addition, the core distance to substrate is adjustable and the sidewall roughness is good. Hence we proceed to analyze the losses theoretically. The various kinds of loss are potentially reducible to 1 dB/cm, except coupling loss on end facets, which is also improvable with the use of proper coupling devices. These demonstrate the potentiality of the platform for on-chip interconnect applications.

Carbon Nanotube Interconnects − A Promising Solution for VLSI Circuits

ABSTRACTIn nanoscale regime, the performance of traditional copper interconnects degrades substantially in terms of latency, power dissipation and induced crosstalk noise. This is due to miniaturization of electronic devices and many-fold enhancement of interconnect lengths in very large-scale integrated (VLSI) circuits. However, carbon nanotubes (CNTs) due to their unique physical properties such as high thermal conductivity, current carrying capability and mechanical strength have drawn the attention of researchers in recent times. The present paper provides comprehensive investigations in the various CNT structures for on-chip VLSI interconnect applications. Different configurations of CNT structures are studied namely single-wall CNT (SWCNT), multiwall CNT (MWCNT) and mixed-wall CNT bundle (MCB). The performance of CNT interconnects is analyzed using driver-interconnect-load system. It is investigated that the reduction in propagation delay in MCB interconnect is nearly 69%, 60%, 40% and 22% as compared to copper, SWCNT bundle, MWCNT and MWCNT bundle interconnect structures, respectively. This analysis considers an interconnect length variation from 500 to 2500 µm for 32-nm technology node. For the same dimensions the overall reduction in power dissipation in MCB interconnect is nearly 60%, 49%, 45% and 36% as compared to copper, SWCNT, MWCNT and MWCNT bundle interconnects, respectively. Furthermore, the effect of crosstalk on the interconnect structures has been examined. It is investigated that MCB has least crosstalk induced delay than all the other interconnect structures. Consequently, it is envisaged that MCB outperforms copper, SWCNT, MWCNT and MWCNT bundle interconnects and are best suited for future VLSI interconnects.

Performance Improvement in SC-MLGNRs Interconnects Using Interlayer Dielectric Insertion

Due to their higher resistance, single layer graphene nanoribbons (GNRs) are not suitable for high-speed on-chip interconnect applications. Hence, we use multilayer GNRs (MLGNRs) that offer multiple conduction channels and lower resistance. However, MLGNRs turn into graphite as the number of layers increase, which reduces the mean-free path of each layer. Insertion of a dielectric between GNR layers prevents its conversion into graphite, thereby improving its mean-free path and scattering rate. In this paper, we are proposing an analytical model for the time-domain analysis of side-contact MLGNRs (SC-MLGNRs) with intermediate dielectric insertion. The proposed model computes scattering rate, mean-free path, and carrier mobility in GNRs where dielectric has been inserted between individual layers. Our analytical results for mobility and scattering rate have been verified with the existing experimental data that exhibit excellent accuracy (maximum of error 4% for mobility and 16% for scattering time). Based on our analysis, we have found that the electron mean-free path in GNRs strongly depends on surrounding dielectric environment. In that, the mean-free path increases with interlayer insertion of high- $k$ dielectrics. Equivalent $RLC$ parameters, delay, energy-delay product, and bandwidth density are calculated for our proposed GNR interconnects using our model. We observe that these performance metrics significantly improve due to the presence of dielectric between GNR layers. When compared with Cu interconnects, insertion of HfO2 between GNR layers results in reduction in both propagation delay and energy-delay product by $2\times $ for interconnect lengths of $1400 ~\mu \text{m}$ . In addition, zigzag SC-MLGNR interconnect with $N=10$ and $\varepsilon _{2}=20$ gives nearly 35% higher bandwidth density than that of Cu interconnects for all interconnect lengths. In our analysis, we propose a new performance metric, bandwidth density/energy-delay product to determine the performance limits of our proposed interconnect structure. Finally, we compare the performance of SC-MLGNR interconnect structure with copper and optical interconnects to exhibit its application in local and global interconnects.

Electrical Modeling of On-Chip Cu-Graphene Heterogeneous Interconnects

In this letter, novel Cu-graphene heterogeneous interconnects are studied by virtue of the equivalent circuit model. The effective resistances of such interconnects are extracted numerically, with the Cu/graphene and graphene/ graphene interface resistances treated appropriately. It is shown that such interconnects can provide superior performance and reliability over Cu wires for an on-chip interconnect applications.

Selective area growth of germanium and germanium/silicon-germanium quantum wells in silicon waveguides for on-chip optical interconnect applications

We propose a robust fabrication process for growing Ge and Ge-based heterostructures in growth windows with Si sidewalls which can be applied to growth in thick Si optical waveguides. Sidewall growth is eliminated by the presence of a dielectric spacer layer which covers the sidewalls. We demonstrate the effectiveness of this process by selective-area growth of Ge and Ge/SiGe quantum wells, and show an improved performance and increased process reliability over previous work.

High-Frequency Behavior of Graphene-Based Interconnects—Part I: Impedance Modeling

This paper presents the first detailed methodology for the accurate evaluation of high-frequency impedance of graphene-based structures relevant to on-chip interconnect and inductor applications. Going beyond the simplifying assumptions of Ohm's law, the effects of electric-field variation within a mean free path and current dependency on the nonlocal electric-field are taken into account to accurately capture the high-frequency behavior of graphene ribbons (GRs). At the same time, a simplified approach that may be adopted at lower frequencies is also explained. Starting from the basic Boltzmann equation and combining with the unique dispersion relation for graphene in its hexagonal Brillouin zone, the current density across the GR structure is derived. First, a semi-infinite slab of GR is analyzed using the theory of Fourier integrals, which is followed by the development of a rigorous methodology for practical finite structures based on a self-consistent numerical calculation of the derived current density using the Green's function approach.

Fast and stable computation of optical propagation in micro-waveguides with loss

The optical propagation in micro-waveguides with loss is described by Helmholtz equation with complex refractive index or wavenumber. In this paper, an improved operator marching method is developed to solve the equation efficiently. This technique can be widely used for microelectronic on-chip interconnect applications.

Ultracompact SOI Microring Add–Drop Filter With Wide Bandwidth and Wide FSR

We report the design and fabrication of an ultracompact silicon-on-insulator add-drop microring filter with a 1.5-mum radius for wavelength-division-multiplexing on-chip interconnect applications. The fabricated device was measured to have a wide free-spectral range of 52 nm and a wide channel bandwidth of 210 GHz, with a 2.9-dB insertion loss and a deep through-port extinction of nearly 25 dB.

Structural and Electrical Characterization of Carbon Nanofibers for Interconnect Via Applications

We present temperature-dependent electrical characteristics of vertically aligned carbon nanofiber (CNF) arrays for on-chip interconnect applications. The study consists of three parts. First, the electron transport mechanisms in these structures are investigated using I-V measurements over a broad temperature range (4.4 K to 350 K). The measured resistivity in CNF arrays is modeled based on known graphite two-dimensional hopping electron conduction mechanism. The model is used because of the disordered graphite structure observed during high-resolution scanning transmission electron microscopy (STEM) of the CNF and CNF-metal interface. Second, electrical reliability measurements are performed at different temperatures to demonstrate the robust nature of CNFs for interconnect applications. Finally, some guidance in catalyst material selection is presented to improve the nanostructure of CNFs, making the morphology similar to multiwall nanotubes.

Expression of Concern: Evaluating the impact of resistance in carbon nanotube bundles for VLSI interconnect using diameter-dependent modeling techniques

Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnects. This paper discusses the modeling of nanotube bundle resistance for on-chip interconnect applications. Based on recent experimental results, the authors model the impact of nanotube diameter on contact and ohmic resistance, which has been largely ignored in previous bundle models. The results indicate that neglecting the diameter-dependent nature of ohmic and contact resistances can produce significant errors. Using the resistance model, it is shown that SWCNT bundles can provide up to one order of magnitude reduction in resistance when compared with traditional copper interconnects depending on bundle geometry and individual nanotube diameter. Furthermore, for local interconnect applications, an optimum nanotube diameter exists to minimize the resistance of the carbon nanotube bundle

Nanofabrication of Vertically Aligned Carbon Nanofibers for Contact Characterization

AbstractRecent studies in nanostructural characterization for on-chip interconnect applications using carbon nanofibers (CNFs) are presented. In this paper, we propose a novel technique, for the purpose of characterizing interfacial structures of vertically aligned CNFs for cross-sectional imaging with scanning transmission electron microscopy (STEM). In this technique, vertically aligned CNFs are selectively grown, by plasma-enhanced chemical vapor deposition (PECVD), on a substrate comprising a narrow strip (width ~100nm) fabricated by focused ion beam (FIB). Using high-resolution STEM, we show that CNFs with diameters ranging from 10 -100 nm exhibit very similar graphitic layer morphologies at the base contact interface.

Structural characteristics of carbon nanofibers for on-chip interconnect applications

In this letter, we compare the structures of plasma-enhanced chemical vapor deposition of Ni-catalyzed and Pd-catalyzed carbon nanofibers (CNFs) synthesized for on-chip interconnect applications with scanning transmission electron microscopy (STEM). The Ni-catalyzed CNF has a conventional fiberlike structure and many graphitic layers that are almost parallel to the substrate at the CNF base. In contrast, the Pd-catalyzed CNF has a multiwall nanotubelike structure on the sidewall spanning the entire CNF. The microstructure observed in the Pd-catalyzed fibers at the CNF-metal interface has the potential to lower contact resistance significantly, as our electrical measurements using current-sensing atomic force microscopy indicate. A structural model is presented based on STEM image analysis.

Investigations of Substrate-Selective Covalent Attachment for Genetically-Engineered Molecular Interconnects

AbstractExperimental investigations are presented regarding the surface-selective molecular selfassembly of fluorinated monochloroalkylsilane of the type (heptadecafluoro-1,1,2,2-tetrahydrodecyl) dimethylchlorosilane (denoted F17) on silicon dioxide (SiO2) and silicon nitride (Si3N4) surfaces. The goal is to investigate the controlled and selective surface self-assembly of these molecules as a potential route for substrate-selective covalent bonding of complex molecular assemblies to semiconductor substrates for on-chip interconnect and device applications. X-ray photoelectron spectroscopy (XPS), x-ray reflectivity (XRR) and atomic force microscopy (AFM) have been used to investigate the selectivity of the F17 self-assembly. Contrary to previous reported results, a high degree of F17 monolayer attachment selectivity is consistently observed between SiO2 and Si3N4 substrates for all three of the aforementioned monolayer characterization methods.

High T c superconductor/noble-metal contacts with surface resistivities in the 10−10 Ω cm2 range

Contact surface resistivities (product of contact resistance and area) in the 10−10 Ω cm2 range have been obtained for both silver and gold contacts to high Tc superconductors. This is a reduction by about eight orders of magnitude from the contact resistivity of indium solder connections. The contact resistivity is low enough to be considered for both on-chip and package interconnect applications. The contacts were formed by sputter depositing either silver or gold at low temperatures (<100 °C) on a clean surface of Y1 Ba2 Cu3 O7−δ (YBCO) and later annealing the contacts in oxygen. Annealing temperature characteristics show that for bulk-sintered YBCO samples there is a sharp decrease in contact resistivity after annealing silver/YBCO contacts in oxygen for 1 h at temperatures above ∼500 °C and gold/YBCO contacts for 1 h above ∼600 °C. Oxygen annealing for longer times (8 h) did not reduce the contact resistivity of silver contacts as much as annealing for 1 h. Auger microprobe analysis shows that indium/YBCO contacts contain a significant concentration of oxygen in the indium layer adjacent to the YBCO interface. Silver and gold contacts, on the other hand, contain almost no oxygen and have favorable interfacial chemistry with low oxygen affinity. Silver also acts as a ‘‘switchable’’ passivation buffer, allowing oxygen to penetrate to the YBCO interface at elevated temperatures, but protecting the YBCO surface at room temperature.