On-chip Domains Research Articles

Accelerating Deep Convolutional Neural Networks Using Number Theoretic Transform

Modern deep convolutional neural networks (CNNs) suffer from high computational complexity due to excessive convolution operations. Recently, fast convolution algorithms such as fast Fourier transform (FFT) and Winograd transform have gained attention to address this problem. They reduce the number of multiplications required in the convolution operation by replacing it with element-wise multiplication in the transform domain. However, fast convolution-based CNN accelerators have three major concerns: expensive domain transform, large memory overhead, and limited flexibility in kernel size. In this paper, we present a novel CNN accelerator based on number theoretic transform (NTT), which overcomes the existing limitations. We propose the low-cost NTT and inverse-NTT converter that only use adders and shifters for on-chip domain transform, which solves the inflated bandwidth problem and enables more parallel computations in the accelerator. We also propose the accelerator architecture that includes multiple tile engines with the optimized data flow and mapping. Finally, we implement the proposed NTT-based CNN accelerator on the Xilinx Alveo U50 FPGA and evaluate it for popular deep CNN models. As a result, the proposed accelerator achieves 2859.5, 990.3, and 805.6 GOPS throughput for VGG-16, GoogLeNet, and Darknet-19, respectively. It outperforms the existing fast convolution-based CNN accelerators up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.6\times $ </tex-math></inline-formula> .

Microfluidic Flow-through SPME Chip for Online Separation and MS Detection of Multiple Analyses in Complex Matrix.

Simplifying tedious sample preparation procedures to improve analysis efficiency is a major challenge in contemporary analytical chemistry. Solid phase microextraction (SPME), a technology developed for rapid sample pretreatment, has flexibility in design, geometry, and calibration strategies, which makes it a useful tool in a variety of fields, especially environmental and life sciences. Therefore, it is important to study the coupling between the microfluidic electrospray ionization (ESI) chip integrated with the solid phase microextraction (SPME) module and the electrospray mass spectrometer (MS). In our previous work, we designed a solid phase microextraction (SPME) module on a microfluidic chip through geometric design. However, automation and calibration methods for the extraction process remain unresolved in the SPME on-chip domain, which will lead to faster and more accurate results. This paper discusses the necessity to design a micromixer structure that can produce different elution conditions on the microfluidic chip. By calculating the channel resistances, the microfluidic chip’s integrated module with the micromixer, SPME, and ESI emitters optimize the geometry structure. We propose the annular channel for SPME to perform the resistances balance of the entire chip. Finally, for SPME on a single chip, this work provides a quantitation calibration method to describe the distribution of the analytes between the sample and the extraction phase before reaching the adsorption equilibrium.

Integrated phase-change photonic devices and systems

Abstract

Tailoring entanglement through domain engineering in a lithium niobate waveguide.

We propose to integrate the electro-optic (EO) tuning function into on-chip domain engineered lithium niobate (LN) waveguide. Due to the versatility of LN, both the spontaneously parametric down conversion (SPDC) and EO interaction could be realized simultaneously. Photon pairs are generated through SPDC, and the formation of entangled state is modulated by EO processes. An EO tunable polarization-entangled photon state is proposed. Orthogonally-polarized and parallel-polarized entanglements of photon pairs are instantly switchable by tuning the applied field. The characteristics of the source are theoretically investigated showing adjustable bandwidths and high entanglement degrees. Moreover, other kinds of reconfigurable entanglement are also achievable based on suitable domain-design. We believe tailoring entanglement based on domain engineering is a very promising solution for next generation function-integrated quantum circuits.

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees

Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today's NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in the network is reduced significantly, which translates to improved network performance or reduced network bandwidth requirements and power consumption. Multiple paths can also be utilized to achieve spatial redundancy, which helps in achieving tolerance against faults or errors in the NoC. A major problem with multipath routing is that packets can reach the destination in an out-of-order fashion, while many applications require in-order packet delivery. In this work, we present a multipath routing strategy that guarantees in-order packet delivery for NoCs. It is based on the idea of routing packets on partially nonintersecting paths and rebuilding packet order at path reconvergent nodes. We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network bandwidth needs and power consumption. We also integrate support for tolerance against transient and permanent failures in the NoC links in the methodology by utilizing spatial and temporal redundancy for transporting packets. Our experimental studies show large reduction in network bandwidth requirements (36.86% on average) and power consumption (30.51% on average) compared to single-path systems. The area overhead of the proposed scheme is small (a modest 5% increase in network area). Hence, it is practical to be used in the on-chip domain.