On-chip Bus Research Articles

SOC chip based smart window curtain design

Relying on the rapid development of embedded systems, it becomes possible to integrate the system hardware into the same chip, and the system on chip SOC (System on Chips) is therefore birthed. This paper will be based on the SOC hardware and software co-design and verification, through the design of intelligent curtains for the specific implementation design of a kind of application in the al-in-one multi-functional machine motherboard design, the motherboard control core using SOC chip, integrated two MCU units, through the main control screen to display the control information to achieve the intelligent window switching conversion switching through the key such as manual mode, timer mode, light control mode. This design uses Keil as the software writing platform to realize the SOC master control system based on the on-chip bus interconnection. As well as this design can effectively reduce the degree of system cumbersomeness and provide smart window design ideas.

Analysis of Dynamic Energy Consumption Sources and Energy Conservation Measures for Bus

This paper focuses on analyzing the influencing factors of bus dynamic energy consumption, providing a bus model related to dynamic energy consumption, as well as the relationship between coupling parameter values and process size changes. By analyzing the calculation formula of bus dynamic energy consumption, measures to reduce bus dynamic energy consumption are pointed out, which is helpful for studying on-chip bus energy conservation issues in deep submicron and nano processes.

On-Chip Bus Protection against Soft Errors

The increasing performance demands for processors leveraged in mission and safety-critical applications mean that the processors are implemented in smaller fabrication technologies, allowing a denser integration and higher operational frequency. Besides that, these applications require a high dependability and robustness level. The properties that provide higher performance also lead to higher susceptibility to transient faults caused by radiation. Many approaches exist for protecting individual processor cores, but the protection of interconnect buses is studied less. This paper describes the importance of protecting on-chip bus interconnects and reviews existing protection approaches used in processors for mission and safety-critical processors. The protection approaches are sorted into three groups: information, temporal, and spatial redundancy. Because the final selection of the protection approach depends on the use case and performance, power, and area demands, the three groups are compared according to their fundamental properties. For better context, the review also contains information about existing solutions for protecting the internal logic of the cores and external memories. This review should serve as an entry point to the domain of protecting the on-chip bus interconnect and interface of the core.

Design and Implementation of IIC Interface IP Core

With the development of SOC (System on Chip) design technology, IPcore reuse technology and on-chip bus technology, which are the basis of SOC design technology, have attracted wide attention from the society. IP core reuse technology can save repetitive work and greatly speed up chip development. At present, China's large-scale SOC design uses more foreign IP cores, which are expensive. IIC(Inter-integrated Circuit) interface is an important peripheral interface in AMBA (Advanced Microcontroller Bus Architecture) bus. It is used for communication between CPU and peripheral devices, and can be used in embedded, radio frequency communication and other fields. Therefore, designing an IIC interface IP has great use value.

Design of an Integrated Cryptographic SoC Architecture for Resource-Constrained Devices

One of the active research areas in recent years that has seen researchers from numerous related fields converging and sharing ideas and developing feasible solutions is the area of hardware security. The hardware security discipline deals with the protection from vulnerabilities by way of physical devices such as hardware firewalls or hardware security modules rather than installed software programs. These hardware security modules use physical security measures, logical security controls, and strong encryption to protect sensitive data that is in transit, in use, or stored from unauthorized interferences. Without mechanisms to circumvent the ever-evolving attacking strategies on hardware devices and the data that they process or store, billions of dollars will always be lost to attackers who ply their trade by targeting such vulnerable devices. This paper, therefore, proposes an integrated cryptographic SoC architecture solution to this menace. The proposed architecture provides security by way of key exchange, management, and encryption. The proposed architecture is based on a True Random Number generator core that generates secret keys that are used in Elliptic Curve Diffie-Hellman Key Exchange to perform elliptic curve scalar multiplication to obtain public and shared keys after the exchange of the public keys. The proposed architecture further relies on a Key Derivation Function based on the CubeHash algorithm to obtain Derived Keys that provide the needed security using the ChaCha20_Poly1305 Authenticated Encryption with Associated (AEAD) Data Core. The proposed Integrated SoC architecture is interconnected by AMBA AHB-APB on-chip bus and the system is scheduled and controlled using the PicoRV32 opensource RISC-V processor. The proposed architecture is tested and verified on the Virtex-4 FPGA board using a custom-designed GUI desktop application.

Embedded firewall for on-chip bus transactions

This article presents a novel approach towards System-on-Chip (SoC) security. Although communications security and operating system hardening have been studied, new application opportunities and menaces have appeared with the incorporation of Multiprocessor-System-on-Chip (MPSoC) into the Internet of Things (IoT). Reliable implementation environments have become necessary, so novel security architectures and solutions have been introduced to protect the vulnerable data, which could be used by plenty of these applications.We propose an Advanced eXtensible Interface (AXI) transaction firewall, which, by checking the type of operation, the physical address, and the bandwidth according to a set of rules, rejects untrusted requests between cores. Results have been performed on a Zynq platform, and obtained results show that the proposed AXI-firewall can prevent unauthorized transactions consuming few hardware resources. Besides, the fully combinational nature of the firewall’s AXI to AXI path entails that the firewall does not affect the overall performance of the system.

An IP Core of AMBA Bus Interface in HDL

The AMBA on-chip bus architecture is a well-known open specification that explains how to connect and manage the functional units that make up a System-On-Chip (SoC). The design and implementation of an AHB Master, RAM, ROM, FIFO and Memory Controller implementation is proposed in this paper. It is primarily divided into two categories: operation initiator (AHB MASTER) and AHB SLAVE. Furthermore, AHB master generate the operation in burst mode, single transfer according to interface requirement and Address generator, generates the address in increment or wrap mode, as well as completing data transfers with an asymmetric asynchronous FIFO with variable data widths for read and write. A bridge between an AHB Master and an AHB slave will be demonstrated using a memory controller, and their outcome in terms of area and speed will be address ed. A finite state machine will be used to design the control framework. Xilinx Virtex 2 XC2VP40 will be used to implement the AHB Master and Slave IP.

Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs

High-Level Synthesis (HLS) dramatically accelerates the design and verification of individual components within larger VLSI systems. With most complex Integrated Circuits (ICs) being now heterogeneous Systems-on-Chip (SoCs), HLS has been traditionally used to design the dedicated hardware accelerators such as encryption cores and Digital Signal Processing (DSP) image processing accelerators. Unfortunately, HLS is a single process (component) synthesis method. Thus, the integration of these accelerators has to be performed at the RT level (Verilog or VHDL). This implies that the system-level verification needs to be performed at lower levels of abstraction, which significantly diminishes the benefits of using HLS. To address this, this work presents a methodology to generate entire heterogeneous SoCs in C. This work introduces two main contributions that enable this: first, an automatic bus generator that generates a synthesizable behavioral description of standard on-chip buses and, second, a library of synthesizable bus interfaces that allow any component in the system to send or receive data through the bus. Moreover, this work investigates the generation of processors and interfaces (peripherals) at the behavioral level as these are important parts of any SoCs, but have long been thought not to be efficiently synthesizable using HLS. Generating complete SoCs in C has significant advantages over traditional approaches. First, it enables the generation of fast cycle-accurate simulation models of the entire SoC, making the verification faster and easier. Second, it allows completely isolating the bus implementation details from the developers’ view, allowing the change between bus protocols with only minor changes in the designers’ code. Thirdly, it allows generating different SoC variants quickly by only changing the HLS synthesis options. Experimental results highlight these benefits.

Optimization of Communication Schemes for DMA-Controlled Accelerators

The hardware accelerator controlled by direct memory access (DMA) is greatly influenced by the communication bandwidth from/to DRAM through on-chip buses. This paper proposes a novel performance estimation algorithm to optimize the communication schemes (CSs), which are defined by the number of direct memory access controllers (DMACs) and the bank allocation of DRAM. In order to facilitate the optimization of CSs, a communication primitive (CP) is defined by the bank allocation and the set of activated DMACs. By using the communication bandwidths of CPs obtained from prior full-system simulations, the proposed performance estimation algorithm can predict the communication performance of CSs more accurately, compared with the conventional performance estimation algorithms. When it is applied to convolutional neural networks (CNNs) and wireless communications (LDPC-coded MIMO-OFDM), the estimation error is measured to be no more than 6.4% and 5%, respectively. In addition, compared with the conventional simulation-based approaches, the proposed estimation algorithm provides a speedup of two orders of magnitudes. The proposed performance estimation algorithm is used to optimize the CS of the CNNs and explore a design space characterized by bank interleaving, outstanding transactions, layer shape, tile size, and hardware frequency. It is shown that the optimized CS improves communication performance by up to 68% for the third convolutional layers of AlexNet and 60% for the MIMO of LDPC-coded MIMO-OFDM. In addition, the DRAM latency is minimized by setting the bank interleaving to the number of outstanding transactions. Moreover, the simulation results show that the optimum CS depends on the application. It is also shown that the use of an extra DMAC does not necessarily improve the communication performance.

Low-power sector-based transition reduction bus encoding technique in SOC interconnects

The data word transmission process on an on-chip bus results in the switching of data bits on bus wires, which charges and discharges the capacitance associated with the wires. Consequently, dynamic power dissipation and increase in delay occurs. Data word transmission is required to change data values that are transmitted over these buses for reducing the transition activity, thereby decreasing the power consumption and delay of the bus. Bus encoding is the commonly used technique to reduce the transition activity of the bus. In this study about the memory bus encoding, i.e., a dynamic sector encoding technique, that is, a sector-based encoding technique is proposed. In this technique, the source word space is divided into a number of sectors with a unique identifier. A dynamic sector (DS) encoder reduces the number of transitions 19.23% more than that reduced by a binary encoder. DS encoding technique is a novel method that reduces the number of transition then reduces the power dissipation and delay when compared to previous encoding techniques which are used in the memory operations.

Design of Advanced High Performance Bus Tracer in System on Chip Using Matrix Based Compression for Low Power Applications

This project proposes multilayer advanced high-performance bus architecture for low power applications. The proposed AHB architecture consists of the bus arbiter and the bus tracer (A.R.M.A., 1999. Specification (Rev 2.0) ARM IHI0011A). The bus arbiter, which is self motivated selects the input packet based on the control signals of the incoming packet. So that arbitration leads to a maximum performance. The On-Chip bus is an important system-on-chip infrastructure that connects major hardware components. Monitoring the on-chip bus signals is crucial to the SoC debugging and performance analysis/optimization (Gu, R.T., et al., 2007. A Low Cost Tile-Based 3D Graphics Full Pipeline with Real-Time Performance Monitoring Support for OpenGL ES in Consumer Electronics. 2007 IEEE International Symposium on Consumer Electronics, June; IEEE. pp.1–6). But, such signals are difficult to observe since they are deeply embedded in a SoC and there are often no sufficient I/O pins to access these signals. Therefore, a straightforward approach is to embed a bus tracer in SoC to capture the bus signal trace and store the trace in on-chip storage such as the trace memory which could then be off loaded to outside world for analysis. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built in compression mechanisms such as dictionary based compression scheme for address and control signals and differential compression scheme for data. To improve the compression ratio matrix based compression which is lossless compression is used instead of differential compression. This system is designed using Verilog HDL, simulated using Modelsim and synthesized using Xilinx software.

Optimized power control using adaptive bus encoding technique in data transmission

Data bits are switched around by using bus wires when data transmission is conducted on an on-chip bus. The data is transmitted through the capsule network, but due to the long routing path, the power is wasted and the data transmission causes a delay. The data bits are transmitted in the capsule network, using wires by switching technique. This switching causes discharging and charging of the capacitance that is associated with the wires. Thus, the delay is increased and then dynamic power dissipation takes place. Sending or receiving data is required to modify data values which are transmitted on the buses for decreasing the switching movement in that way the amount of power consumed by the bus falls and the delay of the on-chip bus. Bus encoding is most commonly used for reducing this bus transition activity. In this study, a probability adaptive bus encoding technique is applied based on a proposed fixed window. The entire window was applied to the transition probability. The average transitional probability condition is used to form a cluster with highly correlated switching patterns. The clustered information is transformed into a grey code. Temporal redundancy in time is utilized in the proposed method for prevent the information loss that occurs during data retrieval. There is an additional power cost because of the circuitry of the encoder and decoder. The cluster efficiency for the proposed encoding technique has been improved by up to 75%. The dynamic power saving is now up to 5%.

A High-Performance Modified AXI Master Slave on-Chip Bus Design and Verification

A High-Performance Modified AXI Master Slave on-Chip Bus Design and Verification

A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era

The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the complex tasks imposed by IoT applications, i.e., augmented reality, artificial intelligence and autonomous driving, within narrow energy and area budgets. However, the new IoT application domain also offers a unique opportunity to revisit and optimize the RISC microarchitectural design flow from a more communication- and memory-centric viewpoint. This manuscript critically explores and optimizes the design of a RISC CPU front-end for IoT delivering a two-fold objective: (i) provide an optimized CPU microarchitecture; and (ii) present a set of three design guidelines to steer the implementation of IoT CPUs. The exploration sits on a newly proposed Systems-on-Chip (SoC) and RISC CPU implementing the RISC-V/IMF ISA and accounting for area, timing, and performance design metrics. Such SoC offers a reference design to evaluate pros and cons of different microarchitectural solutions. A wide combination of microarchitectures considering different branch prediction schemes, cache design architectures and on-chip bus solutions have been evaluated. The entire exploration is focused on the FPGA-based implementation due to the renewed interest for this technology demonstrated by both the research community and companies. We note that ARM launched the DesignStart FPGA program to make available the Cortex-M microcontrollers on Xilinx FPGAs in the form of IP blocks.

An autonomous, highly portable NMR spectrometer based on a low-cost System-on-Chip (SoC).

This paper describes the development of a portable and self-optimizing NMR spectrometer based on a miniaturized custom analog front-end and a System-on-Chip (SoC)-based digital back-end. The SoC integrates a field-programmable gate array (FPGA) fabric with a hard processor running a Linux operating system, thus enabling fully-autonomous operation without the need for an external computer. In the proposed approach, data captured by the FPGA fabric during regular operation is transported to the hard processor using an integrated on-chip bus for further processing. The processed results are then used to automatically estimate parameter values that optimize a suitable cost function, such as signal-to-noise ratio (SNR) per unit time. Finally, the optimized values of both electrical and NMR-related tuning parameters (e.g., preamplifier gain and frequency response, pulse length and amplitude, operating frequency, etc.) are programmed back into the front-end and back-end hardware. Experimental NMR results from various samples in a ∼0.1 T permanent magnet are presented to verify the operation of the proposed spectrometer. These demonstrate on-board Laplace inversion and automated frequency tuning to compensate for temperature changes. Preliminary 14N NQR results are also presented.

Bounds on the Asymptotic Rate for Capacitive Crosstalk Avoidance Codes for On-Chip Buses

Bounds on the Asymptotic Rate for Capacitive Crosstalk Avoidance Codes for On-Chip Buses

Low power driver receiver topology with delay optimization for on-chip bus interconnects

Demands on reducing the delay and power on integrated circuits is increasing with the development of more and more low power devices. The technology scaling and the device design manage static power dissipation. However, the dynamic power dissipation and the delays associated with the bus interconnects have to be addressed separately. A low swing driver-receiver circuit for driving and receiving the signals on the global bus interconnects is presented. Also the capacitively driven interconnects are used for the signal transmission and a series coupling capacitor is introduced at an optimized location along the bus. A substantial improvement of 55% in the delay performance is obtained with the driver-receiver and capacitively driven interconnect topology combine for the data transmission bus

Cooling Codes: Thermal-Management Coding for High-Performance Interconnects

High temperatures have dramatic negative effects on interconnect performance and, hence, numerous techniques have been proposed to reduce the power consumption of on-chip buses. However, existing methods fall short of fully addressing the thermal challenges posed by high-performance interconnects. In this paper, we introduce new efficient coding schemes that make it possible to directly control the peak temperature of a bus by effectively cooling its hottest wires. This is achieved by avoiding state transitions on the hottest wires for as long as necessary until their temperature drops off. We also reduce the average power consumption by making sure that the total number of state transitions on all the wires is below a prescribed threshold. We show how each of these two features can be coded for separately or, alternatively, how both can be achieved at the same time. In addition, error-correction for the transmitted information can be provided while controlling the peak temperature and/or the average power consumption. In general, our cooling codes use $n > k$ wires to encode a given $k$ -bit bus. One of our goals herein is to determine the minimum possible number of wires $n$ needed to encode $k$ bits while satisfying any combination of the three desired properties. We provide full theoretical analysis in each case. In particular, we show that $n = k+t+1$ suffices to cool the $t$ hottest wires, and this is the best possibility. Moreover, although the proposed coding schemes make use of sophisticated tools from combinatorics, discrete geometry, linear algebra, and coding theory, the resulting encoders and decoders are fully practical. They do not require significant computational overhead and can be implemented without sacrificing a large circuit area.

Computing in Memory With Spin-Transfer Torque Magnetic RAM

In-memory computing is a promising approach to addressing the processor-memory data transfer bottleneck in computing systems. We propose spin-transfer torque compute-in-memory (STT-CiM), a design for in-memory computing with spin-transfer torque magnetic RAM (STT-MRAM). The unique properties of spintronic memory allow multiple wordlines within an array to be simultaneously enabled, opening up the possibility of directly sensing functions of the values stored in multiple rows using a single access. We propose modifications to STT-MRAM peripheral circuits that leverage this principle to perform logic, arithmetic, and complex vector operations. We address the challenge of reliable in-memory computing under process variations by extending error-correction code schemes to detect and correct errors that occur during CiM operations. We also address the question of how STT-CiM should be integrated within a general-purpose computing system. To this end, we propose architectural enhancements to processor instruction sets and on-chip buses that enable STT-CiM to be utilized as a scratchpad memory. Finally, we present data mapping techniques to increase the effectiveness of STT-CiM. We evaluate STT-CiM using a device-to-architecture modeling framework, and integrate cycle-accurate models of STT-CiM with a commercial processor and on-chip bus (Nios II and Avalon from Intel). Our system-level evaluation shows that STT-CiM provides the system-level performance improvements of 3.93 times on average (up to 10.4 times), and concurrently reduces memory system energy by 3.83 times on average (up to 12.4 times).

Hiding Hardware Trojan Communication Channels in Partially Specified SoC Bus Functionality

On-chip bus implementations must be bug-free and secure to provide the functionality and performance required by modern system-on-a-chip (SoC) designs. Regardless of the specific topology and protocol, bus behavior is never fully specified, meaning there exist cycles/conditions where some bus signals are irrelevant, and ignored by the verification effort. We highlight the susceptibility of current bus implementations to Hardware Trojans hiding in this partially specified behavior, and present a model for creating a covert Trojan communication channel between SoC components for any bus topology and protocol. By only altering existing bus signals during the period where their behaviors are unspecified , the Trojan channel is very difficult to detect. We give Trojan channel circuitry specifics for AMBA AXI4 and advanced peripheral bus (APB), then create a simple system comprised of several master and slave units connected by an AXI4-Lite interconnect to quantify the overhead of the Trojan channel and illustrate the ability of our Trojans to evade a suite of protocol compliance checking assertions from ARM. We also create an SoC design running a multiuser Linux OS to demonstrate how a Trojan communication channel can allow an unprivileged user access to root-user data. We then outline several detection strategies for this class of Hardware Trojan.