On-chip Block Memories Research Articles

Novel CNN-Based AP2D-Net Accelerator: An Area and Power Efficient Solution for Real-Time Applications on Mobile FPGA

Standard convolutional neural networks (CNNs) have large amounts of data redundancy, and the same accuracy can be obtained even in lower bit weights instead of floating-point representation. Most CNNs have to be developed and executed on high-end GPU-based workstations, for which it is hard to transplant the existing implementations onto portable edge FPGAs because of the limitation of on-chip block memory storage size and battery capacity. In this paper, we present adaptive pointwise convolution and 2D convolution joint network (AP2D-Net), an ultra-low power and relatively high throughput system combined with dynamic precision weights and activation. Our system has high performance, and we make a trade-off between accuracy and power efficiency by adopting unmanned aerial vehicle (UAV) object detection scenarios. We evaluate our system on the Zynq UltraScale+ MPSoC Ultra96 mobile FPGA platform. The target board can get the real-time speed of 30 fps under 5.6 W, and the FPGA on-chip power is only 0.6 W. The power efficiency of our system is 2.8× better than the best system design on a Jetson TX2 GPU and 1.9× better than the design on a PYNQ-Z1 SoC FPGA.

Multiple Cell Upset Injection in BRAMs for Xilinx FPGAs

On-chip block memories (BRAMs) in SRAM-based FPGAs store critical state information as well as user data which need to be protected against radiation-induced upsets. Therefore, reliability evaluation techniques and upset injection in system components are vital. Previous approaches to fault injection in BRAMs are limited in their abilities to create multiple cell upsets (MCUs) (and, in particular, a kind of MCU called multiple bit upsets) and are vulnerable to unintended state corruption in other memory elements when on-chip injectors are used. This letter proposes an efficient approach for multiple upsets emulation in BRAM contents exploiting the configuration memory cells responsible for initialization. The presented methodology ensures safe fault injection in BRAM contents while preserving the state of other memory elements of the design by using a one-time generated partial bitstream. The approach does not require the time-consuming bitstream generation process for every fault but rather uses run-time single-frame modifications for injection purposes.

FPGA Implementation of Range Addressable Activation Function for Lattice-Ladder Neuron

FPGA implementation of hyperbolic tangent activation function for multilayer perceptron structure seems attractive; however, there is a lack of preliminary results on the choice of memory size particularly, when LUT of the function is stored in dedicated on-chip block RAM. The aim of this investigation was to get insights on the distortions of the selected neuron model output by the evaluation of transfer function RMS error and neuron output signal mean and maximum errors while changing the gain and memory size of the activation function. Thus, the range addressable activation function for the second order normalized lattice-ladder neuron was implemented in Artix-7 FPGA. Various gain and memory constrains were investigated. The increase of LUT memory size and gain yielded smaller error of output signal and nonlinear influence on the transfer function. 2 kB of BRAM is sufficient to achieve tolerable less than 0.4 % maximum error utilizing only 0.36 % of total on-chip block memory. DOI: http://dx.doi.org/10.5755/j01.eie.22.2.14598

A real-time sound rendering system based on the finite-difference time-domain algorithm

Real-time sound rendering applications are memory-intensive and computation-intensive. To speed up computation and extend the simulated area, a real-time sound rendering system based on the hardware-oriented finite difference time domain algorithm (HO-FDTD) and time-sharing architecture is proposed and implemented by the field programmable gate array (FPGA) in this study. Compared with the traditional rendering system with parallel architecture, the proposed system extends by about 37 times in the simulated area because data are stored in the on-chip block memories instead of the D flip-flops. The hardware system becomes stable after 400 time steps in the impulse response. To render a three-minute Beethoven classical music clip, the hardware system carries it out in real-time while the software simulation takes about 63 min in a computer with 4 GB RAM and an AMD Phenom 9500 Quad-core processor running on 2.2 GHz.

Hardware Implementation of Rayleigh and Ricean Variate Generators

Compact and fast implementations of digital Rayleigh and Ricean variate generators are presented. Polynomial curve fitting is utilized along with a combination of logarithmic and uniform domain segmentation to provide accuracy, compactness and fast variate generation. A typical instantiation of the proposed Rayleigh generator occupies 124 (<;1%) of the configurable slices, two dedicated multipliers (<;1%), and one on-chip block memory (<; 1%) of a Xilinx Virtex-5 field-programmable gate array (FPGA) and operates at 317 MHz, generating 317 million Rayleigh variates per second. The Ricean variate generator implementation on the same device utilizes 366 (<; 1%) of the logical slices, three on-chip block memories ( <;1%), and 11 (2.8%) of the dedicated multipliers. The application of the Rayleigh and Ricean variate generators is demonstrated in a FPGA-based bit error rate simulator that measures at hardware speeds the symbol error rate performance of a typical wireless communication system over Rayleigh and Ricean fading channels.

A Compact and Accurate Gaussian Variate Generator

A compact, fast, and accurate realization of a digital Gaussian variate generator (GVG) based on the Box-Muller algorithm is presented. The proposed GVG has a faster Gaussian sample generation rate and higher tail accuracy with a lower hardware cost than published designs. The GVG design can be readily configured to achieve arbitrary tail accuracy (i.e., with a proposed 16-bit datapath up to plusmn15 times the standard deviation sigma) with only small variations in hardware utilization, and without degrading the output sample rate. Polynomial curve fitting is utilized along with a hybrid (i.e., combination of logarithmic and uniform) segmentation and a scaling scheme to maintain accuracy. A typical instantiation of the proposed GVG occupies only 534 configurable slices, two on-chip block memories, and three dedicated multipliers of the Xilinx Virtex-II XC2V4000-6 field-programmable gate array (FPGA) and operates at 248 MHz, generating 496 million Gaussian variates (GVs) per second within a range of plusmn6.66sigma. To accurately achieve a range of plusmn9.4sigma, the GVG uses 852 configurable slices, three block memories, and three on-chip dedicated multipliers of the same FPGA while still operating at 248 MHz, generating 496 million GVs per second. The core area and performance of a GVG implemented in a 90-nm CMOS technology are also given. The statistical characteristics of the GVG are evaluated and confirmed using multiple standard statistical goodness-of-fit tests.

Apparatus and system for real-time synthetic focus ultrasonic imaging

An apparatus for use in an ultrasonic imaging system adapted for generating synthetic focus images in real-time. The apparatus employs an integrated circuit architecture which is scalable and can be employed to construct real-time synthetic focus ultrasonic imaging systems having a large number of transducer array elements. The apparatus utilizes one field programmable gate array per image channel for data storage and sub-image generation. Each field programmable gate array includes on-chip block memories to store digitized ultrasonic signal return echo data and at least one block memory used to store data associated with each ultrasonic transmitter-receiver array pair. Logic inside the field programmable gate array calculates memory addresses during image generation to generate a time-of-flight surface and to form sub-images.