On-chip Automatic Tuning Circuit Research Articles

Low-Power Analog Channel Selection Filtering Techniques

Various techniques to reduce power consumption in the channel selection filtering of wireless receivers are discussed. They include class AB operation by the use of quasi-floating gate transistors and reuse of circuital blocks. A mixed continuous/discrete frequency tuning approach set by a simple on-chip automatic tuning circuit is also presented, which allows wide tuning range with modest area and power requirements. The techniques presented are illustrated by a third-order CMOS Gm-C channel filter designed for a dual-mode Bluetooth/ZigBee zero-IF receiver, with two different on-chip automatic tuning circuits. Measurement results for a test chip prototype in a 0.5- $${\upmu }$$μm CMOS process are presented, showing in-band filter IIP3 >20 dBVp with a power consumption of 3.65 mW for both Bluetooth and ZigBee modes, and the required frequency tuning range set by the automatic tuning circuits.

A High <I>Q</I> Gm-C Filter with On-Chip Automatic Tuning Circuit Implemented in Nano-Scale CMOS Process

A High <I>Q</I> Gm-C Filter with On-Chip Automatic Tuning Circuit Implemented in Nano-Scale CMOS Process

A Simple On-Chip Automatic Tuning Circuit for Continuous-Time Filter

A simple on-chip automatic frequency tuning circuit is proposed. The tuning circuit is modified from voltage-controlled filter (VCF) frequency tuning circuit. We utilize an operational transconductance amplifier and a capacitor to from a single-time constant (STC) circuit which can produce a controllable delay time clock to tune the frequency of the filter. It can efficiently reduce the deviations in the 3 dB bandwidth from the variations of PVT (Process, Voltage and Temperature). The design of the STC circuit is simpler than VCF and it has less chip area. The chip has been implanted using TCMC 0.35 μm CMOS technology and the power consumption is less than 9.05 mW.

A widely tunable continuous-time LPF for a direct conversion DBS tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in 0.35 μm SiGe BiCMOS technology. The filter's −3 dB cutoff frequency f0 can be tuned from 4 to 40 MHz. A novel on-chip automatic tuning scheme has been successfully realized to tune and lock the filter's cutoff frequency. Measurement results show that the filter has −0.5 dB passband gain, ±5% bandwidth accuracy, 30 nV/Hz1/2 input referred noise, −3 dBVrms passband IIP3, and 27 dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 13 mA (with f0 = 20 MHz) from 5 V supply, and occupy 0.5 mm2.

A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning

A 4-MHz, fifth-order elliptic low-pass Gm-C filter is described whose characteristics are tuned by an on-chip automatic tuning circuit. The tuning circuit uses only one integrator as the master of tuning instead of problematic voltage controlled oscillator (VCO) and voltage controlled filter (VCF). MOS transistors in linear operation region perform the voltage-to-current conversion in an operational transconductance amplifier, and thereby we achieved /spl plusmn/1.5 V operation. A prototype filter was implemented in a 0.8-/spl mu/m double-poly, double-metal CMOS process. The filter exhibits the dynamic range of 57.6 dB and dissipates 10 mW with /spl plusmn/1.5-V supply. The stopband attenuation is better than 45.0 dB and the passband ripple is smaller than 1.0 dB.

A 4-MHz CMOS continuous-time filter with on-chip automatic tuning

A third-order elliptic low-pass continuous-time filter with a 4-MHz cutoff frequency, integrated in a 3- mu m p-well CMOS process, is presented. The design procedure is based on the direct simulation of a doubly terminated LC ladder filter by capacitors and fully balanced, current-controlled transconductance amplifiers with extended linear range. The on-chip automatic tuning circuit uses a phase-locked loop implemented with an 8.5-MHz controlled oscillator that matches a specific two-integrator loop of the filter. The complete circuit features 70-dB dynamic range (THD<-50 dB) and consumes only 16 mW from +or-2.5-V supplies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>