Omega-gate Nanowire Research Articles

Operational Transconductance Amplifier Designed with Experimental Omega-Gate Nanowire SOI MOSFETs

The nanowire omega-gate technology is one of the possible technologies to replace the FinFET one in the semiconductor chip market. The omega-gate nanowire SOI MOSFET is considered a triple plus gate device, near the gate-all-around performance (figure 1) [1]. Due to the omega gate structure this device presents a better gate to channel electrostatic coupling than the FinFET devices, resulting in a greater immunity to short channel effects [1,2].The Operational Transconductance Amplifier (OTA) is a frequently used analog block in the integrated circuits. The studied OTA consists in a two-stage amplifier, where the first stage is a differential amplifier with active load and the second one is a common source amplifier, as can be seen in figure 2. This analog block is biased through the current source and the bias current is mirrored for each stage. In addition, negative feedback is used between the first and second stages with a compensation capacitor (miller capacitor) in order to stabilize the amplifier response.In this work, an OTA circuit is designed with SOI omega-gate nanowire experimental transistors. In order to find the best device to be used in the project, some measurements were carried out of several nanowire devices with different channel lengths (ranging from 20 nm to 200 nm). The schematic structure of the measured devices is presented in figure 3 [2]. Basic device parameters such as: transconductance (gm), output conductance (gd), Early voltage (VEA), threshold voltage (VT), transistor efficiency (gm/ID) and subthreshold slope (SS) were analyzed.The model of the experimental omega-gate transistors was performed using the Look Up Table (LUT) method. The capacitance measurements of the nanowire transistor were also considered, to simulate the frequency responses more faithfully. The simulator used to design the OTA circuit was Cadence using the Verilog-A language. It was obtained the main figure of merit of this block like voltage gain (Av), gain-bandwidth product (GBW), phase margin and power.A transistor efficiency (gm/ID) near 8 V-1 was chosen in order to compare the performance of OTA designed with omega-gate nanowire devices (NW-OTA) of this work with anothers OTAs designed with triple gate FinFETs (FinFET-OTA) and with nanosheets (NS-OTA) from the literature (Table 1) [3,4].Table 1 shows that the phase margin is close to 60o in all cases, ensuring the stability of the circuit. The NW-OTA presents higher voltage gain compared to FinFET-OTA due to the better gate to channel coupling. The NS-OTA presents the highest voltage gain of all cases, but it is the more expensive technology [4]. When GBW is analyzed for all 3 designs, the NW-OTA shows better results than the NS-OTA, using the same load capacitance of 200fF, thanks to the lower miller capacitance (Cc) required to keep the frequency behavior. The FinFET-OTA shows the best result in relation to GBW, but the FinFET-OTA project doesn’t consider a load capacitance, making the comparison unfair [3].Figure 4 shows the gain and phase of the OTA using a SOI omega-gate nanowire transistors.In summary, the OTA designed with SOI omega-gate nanowire technology presents a better performance than FinFET one, can be implemented in a smaller area on the chip (smaller Cc capacitor and smaller number of fins in parallel) and it is a cheaper option compared to nanosheet one. Figure 1

Operational Transconductance Amplifier Designed with Experimental Omega-Gate Nanowire SOI MOSFETs

Operational Transconductance Amplifier (OTA) designed with Omega-gate Nanowire SOI MOSFETs was evaluated. The transistor model was created using Verilog-A language and a Look-Up Table strategy, which is based on very precise measurements of the fabricated device. For the model, both the current and capacitance responses were considered. The proposed OTA showed a very good results with a voltage gain of 69.5 dB and a gain–bandwidth product (GBW) of 724 MHz. After that, a comparison among OTAs using different technologies was performed, showing that although the OTA designed with omega gate nanowire does not reach the same voltage gain of one designed with nanosheets, the proposed OTA shows a better GBW and smaller compensation capacitor for the same load capacitance. Considering the complexity of the nanosheet manufacture and the cost, the OTA designed with W-gate nanowire appears as a promising solution to replace FinFETs in the future.

Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature

In this work the gate-all-around nanosheet transistor is analyzed at high temperatures, from analog point of view. At first, the gate-all-around nanosheet (NS) behavior is compared with reported omega-gate nanowire (NW) transistors, at room temperature. It is worth noting that the nanosheets devices present a stronger electrostatic coupling between gate and channel (lower short channel effect -SCE), and higher intrinsic voltage gain, AV (better Early voltage) when compared with NW devices (60 dB for NS and 55 db for NW, with L = 200 nm). Therefore, the second part of this work focuses on the analog study only for NS transistors (with different metal gate stacks), presenting the trade-off between transistor efficiency and unit gain frequency, fT from room temperature to 200 °C. The obtained results are very promising for both gate stack transistors, where values of transistor efficiency about 37 V−1 (T = 25 °C and L = 200 nm) and fT about 260 GHz (T = 25 °C and L = 28 nm) are obtained. The optimal application point was obtained at the transition from moderate to strong inversion.

Equivalent DG Dimensions Concept for Compact Modeling of Short-Channel and Thin Body GAA MOSFETs Including Quantum Confinement

In this work, short-channel effects (SCEs) in cylindrical gate-all-around (GAA) MOSFETs with intrinsic or lightly doped channels are analytically described by using the conformal mapping technique for 2-D double-gate (DG) FETs. An equivalent capacitor model leads to an equivalent channel length concept, which allows to correctly determine the SCEs relevant center and surface potentials ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Phi _{{C}} $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Phi _{{S}} $ </tex-math></inline-formula> ) at the potential barrier. Furthermore, we make use of the rotational symmetry of GAA FETs and modify a compact drain current model of a DG device to use it for GAA transistors. Also, a mathematical correlation regarding quantum confinement for thin body transistors is derived, which shows that the mostly unwanted quantum effects occur in GAA structures already for thicker channels compared to DG transistors. Both transistor types experience a comparable influence with regard to quantization if the channel thickness of GAA FETs is 53% more than that of DG FETs. The dc behavior of our adapted model is verified with 3-D TCAD simulation data and applied to experimental data of ultrascaled silicon on insulator (SOI) omega-gate nanowire N-MOSFETs.

Analysis of the Negative-Bias-Temperature-Instability on Omega-Gate Silicon Nanowire SOI MOSFETs with Different Dimensions

This work presents an experimental andThis work presents an experimental and simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation. simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation.

Reduction of random telegraph noise by high-pressure deuterium annealing for p-type omega-gate nanowire FET

In this work, we studied the effect of high-pressure deuterium annealing (HPDA) on a p-type omega-gate nanowire field effect transistor by random telegraph noise (RTN) signal analysis. After HPDA under conditions of 400 °C and 10 atm for 30 min, IOFF decreases by 41.2% and ION increases by up to 5.4%. Also, subthreshold swing (SS) is reduced from 72 mV dec−1 to 70 mV dec−1. In RTN analysis, multi-level RTN is reduced to single-level RTN due to the passivation of a fast trap site by HPDA. ΔID/ID is also decreased 1.3 and 1.1 times at |VOV| = 0.2 V and 0.4 V, respectively. From the low-frequency noise analysis, the reduction of trap density is observed by 86% at |VOV| = 0.4 V after HPDA. Through these results, we found that the HPDA reduces traps of gate dielectric and improves the quality of the interface between gate dielectric and NW channel in p-type OGNW FET.

Analysis of Omega-Gate Nanowire SOI MOSFET Under Analog Point of View

This paper presents an evaluation of omega-gate nanowire n- and p-type SOI MOSFETs performance focusing on the main analog figures of merit. The different channel widths (WNW) and channel lengths (L) were also evaluated. These devices presented values of subthreshold slope near the theoretical limit at room temperature (60 mV/dec) and in the worst case a DIBL value smaller than 70 mV/V showing its immunity to short channel effects (SCEs) in the range studied. The narrowest device showed great electrostatic coupling, improving transconductance (gm), presenting an unit gain frequency over 200 GHz and intrinsic voltage gain over 80 dB. These values suggests that this device is capable of achieving good performance on new applications such as 5G communications and Internet-of-Things (IoT).

Analysis of Omega-Gate Nanowire Devices from Parasitic Conduction to Ionizing Radiation Effects

The proposal of this work is to present an analysis of omega-shaped-gate silicon nanowire field-effect-transistors operating in the subthreshold region. It is analyzed three channel widths (WNW), 220, 40 and 10 nm. In the widest device is noted a back interface conduction that it was extrapolated through numerical simulations adding the positive fixed charges (Qox) and interface traps (Nit) at the interface between the channel and the buried oxide. While studying the effects of these charges, it is noticed that besides causing a threshold voltage (VT) shift it does not present a significant variation in the subthreshold swing (SS). Since the total ionizing dose can be simulated by adding Nit and Qox in the gate and buried oxides, this study is extended, aiming to analyze the impact of ionizing radiation in the subthreshold region of nanowire devices. The nanowires presents a high immunity in SS due to the supercoupling provided by the small silicon height (hfin), which is confirmed through the analysis of the surface electrostatic potential. The hfin increase results in a worst coupling and, the Nit and Qox degrades the SS while increasing WNW. For WNW = 10 nm even with hfin = 65 nm, no significant influence in SS is observed.

Assessment of technological and geometrical device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs

A study of the gate oxide/channel interface quality in ultra-scaled SOI omega-gate nanowire NMOS FETs with cross-section as small as 10nm×10nm is experimentally presented by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, additional hydrogen anneal, or channel orientation difference. A method for rigorous contribution assessment of the two oxide/channel interfaces (top surface vs. side-walls) is also demonstrated. Quality of the interface is slightly altered among the 4-types of technological parameters and the structural variety down to nanowire. However, an excellent quality of Hf-based high-k/metal gate stack is observed and sustained in all the devices. In particular, efficient tensile strain stressor is demonstrated with high enhancement of the NMOS FET performance and preserved 1/f noise performance fulfilling the requirement for future CMOS logic node stated in the international technology roadmap for semiconductors.

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

A detailed study of performance in uniaxially strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial strained-SOI (sSOI) substrate is presented. Two-dimensional strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. An improvement of electron mobility in sSOI NW scaled down to 10-nm width is successfully demonstrated (+55 % with respect to SOI NW) due to remaining uniaxial tensile strain. This improvement is maintained even by using hydrogen annealing to form an Omega gate. For short gate length, a strain-induced <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> gain as high as +40% at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LG</i> = 45 nm is achieved for a multiple-NW active pattern.