Off-line Built-in Self-test Research Articles

An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set

Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of on-line techniques that circumvent the problems appearing separately in on-line and in off-line BIST. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic off-line and concurrent online. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper a novel input vector monitoring concurrent BIST scheme based on a pre-computed test set is presented. The proposed scheme can perform both concurrent on-line and off-line testing; therefore it can be equally well utilized for manufacturing and concurrent on-line testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing.

Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures

Built-in Self Test (BIST) is increasingly being used in production testing of VLSICs. In BIST, extra logic is implemented to generate test patterns and compact test responses on chip. However, this extra logic is used only during the test mode. Traditionally, BIST structures used for on-line testing have been different from the BIST structures used for off-line production testing. Replicated hardware, comparators and checkers are typical on-line BIST structures. This is because on-line BIST techniques are mostly based on space or time or information redundancy. On the other hand, typical off-line BIST structures include linear feedback shift register (LFSR) based pattern generators and multiple input signature register (MISR) based test response compactors. In this paper we report a Versatile BIST approach (VBIST) that targets both off-line and on-line self test. VBIST uses off-line BIST circuitry for on-line testing as well. Unlike traditional on-line self test approaches, VBIST does not use functional data as test inputs. Rather, VBIST generates test patterns and compacts test responses during the normal mode of operation. Furthermore, VBIST coordinates this generation and application of test patterns and compaction of test responses with the usage profile of the modules in the design. VBIST entails little additional impact on performance and area of the design (vis-a-vis the performance and area of a design with off-line BIST). We validated the proposed approach using the Synopsys Behavioral Compiler as the synthesis framework and by writing synthesis scripts for incorporating VBIST constraints.