OFF Leakage Research Articles

Electron Mobility Enhancement in GeSn n-Channel MOSFETs by Tensile Strain

A record high electron mobility of 698 cm2/ $\text{V}\cdot \text{s}$ in a tensile-strained Ge0.96Sn0.04 nMOSFET is demonstrated in this letter. High-quality GeSn films were epitaxially grown by low-temperature chemical vapor deposition. Different strain conditions in the active GeSn layers were achieved by Ge or GeSn relaxed buffers. A mesa FET structure was used to effectively reduce the OFF leakage by a recessed p/n junction in Ge. The ION/IOFF ratio in the mesa GeSn FETs is boosted by a factor of 100 compared to conventional planar devices. As the GeSn film becomes more tensile strained, the channel mobility is enhanced, which could be attributed to a higher carrier population in the ${\Gamma }$ valley.

Synchronous Circuit Design With Beyond-CMOS Magnetoelectric Spin–Orbit Devices Toward 100-mV Logic

The supply voltage scaling has become increasingly challenging in the advanced CMOS technology due to the threshold voltage requirement for transistor OFF leakage, limiting the system energy efficiency. Spintronic logic utilizes the physical quantity of magnetization or spin as a computation variable, offering new design paradigms in terms of ultralow voltage operation and nonvolatility, but suffering from switching inefficiency of the charge-to-spin conversion. The magnetoelectric spin–orbit (MESO) device has been proposed as a new alternative logic device candidate to solve these issues by magnetoelectric transduction using a novel multiferroic oxide [both ferroelectric (FE) and antiferromagnetic], a ferromagnet and a spin injection layer. It enables a path toward 10–100 $\times $ switching energy reduction compared to CMOS inverter in 2018 node, due to the device and material innovations of a novel switching mechanism. In this paper, in order to build a MESO logic family for new circuit and architecture exploration, we propose for the first time the fundamental building blocks such as MESO sequential and combinatorial circuits for the synchronous logic operation. We employ a transistor sharing and a novel multiphase clocking scheme to address the circuit design issues such as clock control, directionality of state propagation, and power gating and enable the design exploration for MESO digital logic. Based on the proposed circuit techniques, we demonstrate these MESO logic functions operating at a supply voltage of 100 mV and a clock period of 1.2 ns with 320-ac FE polarization through the circuit simulations.

A high electrical performance of DG-MOSFET transistors in 4H-SiC and 6H-SiC 130 nm technology by BSIM3v3 model

Abstract In this paper, the electrical performance of double gate DG-MOSFET transistors in 4H-SiC and 6H-SiC technologies have been studied by BSIM3v3 model. In which the I–V and g m–V characteristics and subthreshold operation of the DGMOSFET have been investigated for two models (series and parallel) based on equivalent electronic circuits and the results so obtained are compared with the single gate SG-MOSFET, using 130 nm technology and OrCAD PSpice software. The electrical characterization of DG-MOSFETs transistors have shown that they operate under a low voltage less than 1.2 V and low power for both models like the SG-MOSFET transistor, especially the series DG-MOSFET transistor is characterized by an ultra low power. The different transistors are characterized by an ultra low OFF leakage current of pA order, very high ON/OFF ratio of and high subthreshold slope of order 0.1 V/dec for the transistors in 6H-SiC and 4H-SiC respectively. These transistors also proved higher transconductance efficiency, especially the parallel DG-MOSFET transistor.

Effects of In-Situ Plasma-Enhanced Atomic Layer Deposition Treatment on the Performance of HfO2/In0.53Ga0.47As Metal-Oxide-Semiconductor Field-Effect Transistors

In-situ plasma-enhanced atomic layer deposition (PEALD) technique was employed for device passivation to realize a high-performance inversion-mode HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As metal-oxide-semiconductor field-effect transistor (MOSFET). Excellent quality of gate dielectric is enabled by utilizing the PEALD-aluminum nitride as a pre-gate interfacial layer, followed by a post-gate remote-plasma gas treatment. In-situ PEALD treatment led to enhanced dc characteristics, such as drain current, peak transconductance, subthreshold swing, OFF leakage current, and effective electron mobility. X-ray photoelectron spectroscopy analysis indicates a reduction of In- and Ga-related signals. Furthermore, small drain current hysteresis and low-interface state density (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) value confirm a high interfacial quality for the high-k/III-V structure. Overall, the PEALD passivation for HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As interface shows a remarkable improvement on the MOSFET performance.

A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS

This paper presents a pipelined analog-to-digital converter (ADC) operating from a 0.5-V supply voltage. The ADC uses true low-voltage design techniques that do not require any on-chip supply or clock voltage boosting. The switch OFF leakage in the sampling circuit is suppressed using a cascaded sampling technique. A front-end signal-path sample-and-hold amplifier (SHA) is avoided by using a coarse auxiliary sample and hold (S/H) for the sub-ADC and by synchronizing the sub-ADC and pipeline-stage sampling circuit. A 0.5-V operational transconductance amplifier (OTA) is presented that provides inter-stage amplification with an 8-bit performance for the pipelined ADC operating at 10 Ms/s. The chip was fabricated on a standard 90 nm CMOS technology and measures 1.2 mm times 1.2 mm. The prototype chip has eight identical stages and stage scaling was not used. It consumes 2.4 mW for 10-Ms/s operation. Measured peak SNDR is 48.1 dB and peak SFDR is 57.2 dB for a full-scale sinusoidal input. Maximal integral nonlinearity and differential nonlinearity are 1.19 and 0.55 LSB, respectively.

Formation of low-resistivity poly-Si and SiN x films by Cat-CVD for ULSI application

In this paper, bulk-Si metal–oxide–semiconductor field effect transistors (MOSFETs) are fabricated using the catalytic chemical vapor deposition (Cat-CVD) method as an alternative technology to the conventional high-temperature thermal chemical vapor deposition. Particularly, formation of low-resistivity phosphorus (P)-doped poly-Si films is attempted by using Cat-CVD-deposited amorphous silicon (a-Si) films and successive rapid thermal annealing (RTA) of them. Even after RTA processes, neither peeling nor bubbling are observed, since hydrogen contents in Cat-CVD a-Si films can be as low as 1.1%. Both the crystallization and low resistivity of 0.004 Ω·cm are realized by RTA at 1000 °C for only 5 s. It is also revealed that Cat-CVD SiN x films prepared at 250 °C show excellent oxidation resistance, when the thickness of films is larger than approximately 10 nm for wet O 2 oxidation at 1100 °C. It is found that the thickness required to stop oxygen penetration is equivalent to that for thermal CVD SiN x prepared at 750 °C. Finally, complementary MOSFETs (CMOSs) of single-crystalline Si were fabricated by using Cat-CVD poly-Si for gate electrodes and SiN x films for masks of local oxidation of silicon (LOCOS). At 3.3 V operation, less than 1.0 pA μm −1 of OFF leakage current and ON/OFF ratio of 10 7–10 8 are realized, i.e. the devices can operate similarly to conventional thermal CVD process.

OFF-State leakage current mechanisms in bulkSi and SOI MOSFETs and their impact on CMOS ULSIs standby current

In this work, an analytical model of the OFF-state leakage current in metal-oxide-semiconductor (MOS) transistors and its relation with the standby current of logic complementary MOS (CMOS) ICs is presented. The OFF leakage currents in (1) bulk MOS; (2) floating-body silicon-on-insulator (FB-SOI); and (3) body-tied SOI (BT-SOI) MOS field effect transistors (MOSFETs) are modeled based on physics mechanisms, equivalent circuits and operational block diagrams. Good correlation is obtained between the theory and experimental devices. The model clarifies and quantifies that in thin film FB-SOI, the OFF leakage current is dominated by (a) V/sub th/ at drain voltages lower than the onset of the "kink" effect V/sub ds/<V/sub dk/, and (b) the impact ionization-induced floating-body effect for V/sub ds/>V/sub dk/. The OFF-state leakage current model is successfully applied to the analysis and prediction of the leakage current components in logic integrated circuits (CMOS ICs).