Off-axis Wafers Research Articles

Photoelastic Characterization of Residual Strain Distribution in Commercial Off-Axis SiC Substrates

Two-dimensional distribution of strain-induced birefringence has been selectively characterized in commercial 4° off-axis wafers of 4H-silicon carbide (SiC) crystal by using an originally-developed imaging polariscope. The natural birefringence, which is often observed in uniaxial crystals, was eliminated by optimizing the light incident angle so that the light propagates parallel to the c-axis inside the crystal. The eliminated natural birefringence was at least twice as large as that of the strain-induced ones, which demonstrates the validity of the elimination process. A typical retardation map under optimal incidence revealed various distributions of strain-induced birefringence, such as local concentrations due to the structural crystal defects and gradual increase or relief due to the thermal stress during the crystal growth and cooling processes. The maximum retardation was 0.28, which corresponds to 7.6 × 10−5 in strain terms, and 30 MPa in stress terms. Because of its sufficient sensitivity to the strain-induced birefringence and elimination capability in the natural birefringence, it is concluded that our technique is useful to characterize the residual strain distribution in commercial off-axis SiC substrates.

Low Defect Thick Homoepitaxial Layers Grown on 4H-SiC Wafers for 6500 V JBS Devices

70-um thick homoepitaxial layers with very low defect density were grown on 6-inch 4° off-axis wafers using hot-wall chemical vapor deposition (CVD). Process optimization resulted in reduction of the density of triangular defects from 1.01 cm-2 to 0.14 cm-2. The treatment of wafer (CMP or selection) was essential. The in-situ etch process was optimized prior to the epitaxial growth. Junction Barrier Schottky diodes fabricated on the epitaxial films presented a typical I–V characteristic and a block voltage of 6500 V.

Development of Solvent Inclusion Free 4H-SiC Off-Axis Wafer Grown by the Top-Seeded Solution Growth Technique

This study reports our newly developed technology for SiC solution growth. In particular, we succeed in completely suppressing solvent inclusions, which have been a serious technological problem peculiar to the solution growth method. Then, we fabricate two-inch-diameter 4° off-axis SiC wafers without solvent inclusions. Moreover, we performed their crystal defects evaluation. It was found that our wafers were low resistance n-type 4H-SiC and contain almost no basal plane dislocation. As a result, the superior quality of our solution-grown crystal was confirmed.

Dislocation Analysis of 4H-/6H-SiC Single Crystals Using Micro-Raman Spectroscopy

Micro-Raman spectroscopy is an excellent non-destructive analysis method, which compensates for disadvantages of KOH method. Raman shift of A1(LO) and E1(TO) band at threading screw dislocation(TSD) were investigated in n-type on/off-axis 4H- and 6H-SiC single crystal wafers by Micro-Raman scattering at room temperature. The results showed that A1(LO) band were shifted toward higher frequency while the E1(TO) band were shifted toward lower frequency on the on-axis wafers. The shifts are caused by increasing electron concentration and lattice disorder near the dislocation core, respectively. In the off-axis wafers, no shifts were observed possibly due to the measurement geometry which does not contain whole dislocation core.

Selective Area Growth of InP on On-Axis Si(001) Substrates with Low Antiphase Boundary Formation

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four side-walls of the Shallow Trench Isolation. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

Volume production of high quality SiC substrates and epitaxial layers: Defect trends and device applications

We review the progress of silicon carbide (SiC) bulk growth by the sublimation method, highlighting recent advances at Dow Corning, which resulted in the commercial release of 100mm n-type 4H-SiC wafers with median micropipe densities (MPD) in production wafers <0.1cm−2 and the demonstration of micropipe free material over a full 100mm diameter. Investigations by Synchrotron White Beam X-ray Topography (SWBXRT) and molten KOH etch pit analysis of 100mm wafers demonstrate threading screw dislocation densities <500cm−2. Additional results indicate the positive impact of maintaining thermo-mechanical stress levels in the growing crystal below the critical resolved shear stress on reducing basal plane dislocation densities to values as low as ∼300–400cm−2 in 100mm crystals. We summarize the steps of systematic quality improvements on increasing wafer diameter, utilizing numerical simulations of the SiC growth system as a critical tool to guide this process. For the economical production of SiC epitaxy, a 10×100mm wafer platform has been established in a warm-wall planetary chemical vapor deposition (CVD) reactor. The combined improvements in the epitaxy process, pre-epi wafer surface preparation and the underlying substrate quality itself have led to a reduction of the device killer defect density from 8cm−2 to 1.5cm−2 on a volume product like 100mm 4° off-axis 6.5μm epi-wafers. Dow Corning production epi-wafers routinely show Schottky diode yields above 90% at a die size of 2mm×2mm. Additionally, 50–100μm thick epitaxy on 76mm 4° off-axis wafers with morphological defect densities of 2–6cm−2, a surface roughness (RMS) ≤1nm as measured by atomic force microscopy (AFM), and carrier lifetimes consistently in the range of 2–3μs has been demonstrated.

(Invited) Selective Area Growth of InP on On-Axis Si(001) Substrates with Low Antiphase Boundary Formation

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation mechanism during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four STI side-walls. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

Electron mobility in scaled silicon metal-oxide-semiconductor field-effect transistors on off-axis substrates

Off-axis silicon wafers promise monolithic integration of III-V optoelectronics with silicon microelectronics. However, it is unclear how miniaturization affects electronic device performance on off-axis substrates. We present the fabrication and characterization of metal-oxide-semiconductor field-effect transistors (MOSFETs) with different gate lengths on regular Si(100) and 4° off-axis wafers. The field-effect electron mobility in the off-axis devices is lower than in their (100)-wafer counterparts with equivalent gate length. Monte Carlo simulations have reproduced the experimental data and demonstrated that the mobility degradation in off-axis devices stems from enhanced electron scattering from the Si/SiO2 surface roughness. Short-channel MOSFETs on (100) and off-axis substrates perform comparably.

Damage-Free Planarization of 2-Inch 4H-SiC Wafer Using Pt Catalyst Plate and HF Solution

We report a damage-free and efficient planarization process for silicon carbide (SiC) using platinum as a catalyst in hydrofluoric acid (HF) solution. In previous studies, 4H-SiC (0001) on-axis wafers were planarized by this process and an extremely flat surface was obtained. However, electronic device substrates require off-axis wafers. In the present study, 4H-SiC (0001) 8° off-axis Si-face wafers were planarized using a Pt catalyst plate and HF solution. In the first trial using these wafers, the surface roughness worsened and a diagonal pattern was observed by phase-shift interference microscopy. The pattern seemed to have been formed when the Pt plate morphology was transcribed onto the wafer. The removal rate of the 8° off-axis Si-face wafer is much greater than that of the on-axis Si-face wafer. Thus, we concluded that the use of a smoother catalyst plate would be necessary to obtain a smooth 8° off-axis Si-face wafer surface. Improving the Pt plate morphology by hand lapping also improved the surface roughness of the processed wafer as compared with the preprocessed surface. The maximum height of the surface irregularity (peak-to-valley, P-V) and root-mean-square roughness were improved to 0.513 nm and 0.044 nm, respectively, as determined by atomic force microscopy (2×2 μm2).

Anisotropic Etching of Silicon as a Tool for Creating Injection Molding Tooling Surfaces

To improve the fidelity of the microinjection molding process, research is underway to implement silicon inserts as tooling surfaces in an injection molding machine. These tooling surfaces are created using typical microfabrication processes, such as bonding and chemical etching. The primary focus of this paper is the evaluation of anisotropic wet etching of off-axis silicon wafers, including experimental results and simulations. A method is presented for the determination of the lang110rang direction and subsequent alignment of the mask with an accuracy of 0.01deg. The use of atomistic kinetic Monte Carlo simulations reveals the extreme importance of proper alignment between the mask features and the off-axis wafer. As an example application, the fabrication steps and corresponding simulations of a silicon insert for the manufacture of disposable plastic razors are presented

The Effect of Thermal Gradients on SiC Wafers

An in-situ curvature measurement equipment has been used to measure the curvature change of 4H-SiC 8degrees off-axis wafers, both with and without a CVD grown epitaxial layer, under beat treatments ...

SiC epitaxial growth on porous SiC substrates

ABSTRACTWe report on the growth and crystal quality of CVD epitaxial layers grown on porous SiC (PSC) substrates. A layer of porous SiC was fabricated by surface anodization of commercial 4H and 6H-SiC (0001)Si face off-axis wafers. The 4H and 6H-SiC epilayers were grown on porous SiC (PSC) substrates using atmospheric pressure CVD at 1580°C and a Si to C ratio of 0.3. Results of X-ray diffraction, RHEED, SEM and AFM characterization demonstrated good surface quality of the films grown on porous material. PL data indicate a greatly improved defect structure in the epi layers grown on PSC as compared to control samples. Preliminary etch pit experiments to estimate the dislocation density indicate a three-fold reduction in defect density in the epi material grown on PSC substrates as compared to epi grown conventional substrates.

Structural Characterization Of Sic Epitaxial Layers Grown On Porous Sic Substrates

ABSTRACTA layer of porous SiC was fabricated by surface anodization of commercial 4H and 6H-SiC (0001)Si face off-axis wafers. A 8.5 μm 4H–SiC epilayer was grown on porous SiC (PSC) substrates using atmospheric pressure CVD. TEM investigation on cross-sectional specimens of the CVD epitaxial layers revealed that the presence of pores in the substrate does not lead to the formation of any micropipe in the epitaxial layer. The investigation also failed to detect a more than usual dislocation density on the basal plane of the epitaxial layer. Based upon the results of various analytical techniques applied to the CVD deposit we propose that the density of screw dislocations in the epitaxial layer is less than 5–104 cm−3. It should be noted that the density of similar types of dislocations in the initial substrate as determined by the TEM was ∼106 cm−3, so this preliminary investigation indicates that the epitaxial layer grown on PSC may have a reduction in dislocation density of more than an order of magnitude over those grown on conventional SiC substrates that are not porous. Synchrotron white beam x-ray topography (SWBXT) was performed on these layers. Comparison between the dislocation density on the porous and standard epitaxial layers proved to be very similar using this technique.