Occurrence Of Intermittent Faults Research Articles

On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines

Voltage droop is a major reliability concern in nano-scale very large-scale integration designs. Undesirable voltage droop is often a result of excessive IR drop. On the other hand, Ldi/dt -induced droop occurs when logic gates in the circuit draw high-switching current from the on-chip power supply network, and this problem is exacerbated at high-clock frequencies and smaller technology nodes. A consequence of voltage droop is usually an increase in path delays and the occurrence of intermittent faults during circuit operation. The addition of conservative timing margins, also known as guardbands, is a common practice to tackle the problem of voltage droop. However, such static and pessimistic guardbands, which are calculated at design time based on worst-case conditions, lead to significant performance loss. Dynamic frequency scaling is an alternative approach that enables the dynamic adjustment of clock frequency based on the actual voltage droop seen during runtime. For dynamic voltage-frequency to be effective, accurate and real-time prediction of voltage droop is essential. We propose a support-vector machine (SVM)-based regression method to predict voltage droop due to pattern-dependent IR drop based on inputs to the chip at runtime. Moreover, we reduce the amount of data needed for accurate prediction by using correlation-based feature selection. Several benchmarks from ITC’99 and International Work on Logic and Synthesis’05 highlight the effectiveness of the proposed method in terms of delay-prediction accuracy. Since real-time droop prediction requires hardware implementation of the predictor, we present the hardware design and synthesis results to demonstrate that the hardware overhead for the SVM predictor is negligible for large circuits.

High frequency modeling of a shielded four-core low voltage underground power cable

Underground low voltage (LV) power cables have a long life span, and so far minimum effort was put in methods for condition assessment. However, a slow but steady increase in the amount of faults is being observed and future de-central power generation may further put pressure on the reliability of the LV grid. Therefore, condition monitoring for LV cable systems is under investigation. With the occurrence of intermittent faults, fast transients from discharges may be observed before an outage occurs. To estimate if such signals are measurable, a model of the cable valid up to 50 MHz was derived. Numerical simulations have been used to obtain the parameters of the multi-conductor transmission line model, with special consideration of the copper screen configuration. Measurements on a 60 m cable segment have been performed to verify the model, showing good agreement. This model will be used to investigate signal propagation through a LV grid with focus on the feasibility to base LV condition monitoring on signals which may originate from upcoming cable faults.