Observability Do N't Care Research Articles

Computing Observability of Gates in Combinational Logic Circuits by Bit-Parallel Simulation

The article considers vector computation methods (bit-parallel simulation) for determining the observability of combinational logic gates. The computations produce an ODC (observability don’t care) set of all gates for a given set of circuit states. These results make it possible to evaluate the probability of logical masking of a random circuit fault. The methods are compared by accuracy and time costs using testing results for ISCAS ’85 benchmark circuits.

Performance Improvement and Power Consumption Reduction of an Embedded RISC Core

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 μm technology library is reduced by 16%.

임베디드 RISC 코어의 성능 및 전력 개선

본 논문에서는 임베디드 RISC 코어의 성능 및 전력 소모 개선을 위해 동적 분기예측 구조, 4원 집합연관 캐쉬 구조, ODC 연산을 이용한 클록 게이팅 기법을 제시한다. 동적 분기 예측 구조는 분기 명령에 대해 다음에 실행될 명령에 대한 예측 주소를 저장하는 BTB (Branch Target Buffer)를 사용한다. 4원 집합연관 캐쉬는 네 개의 메모리 블록을 한 개의 캐쉬 블록에 사상되는 구조로서 직접사상 캐쉬에 비해 접근 실패율이 낮고 라인 교체 방식으로 Pseudo-LRU 방식을 채택하여 LRU 정보를 저장하는 비트 수를 감소시킨다. ODC를 이용한 클록게이팅 기법은 논리합성 개념인 무관조건의 입출력 ODC 조건을 찾아 클록 게이팅 로직을 삽입함으로써 동적 소비전력을 줄인다. 제시한 구조들을 임베디드 RISC 코어인 OpenRISC 코어에 적용하여 성능을 측정한 결과, 기존 OpenRISC 코어 대비 실행시간이 약 29% 향상 되었고, Chartered <TEX>$0.18{\mu}m$</TEX> 라이브러리를 이용하여 동적 전력을 측정한 결과, 기존 OpenRISC 코어 대비 소비전력이 16% 이상 감소하였다. This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of embedded RISC core and a clock-gating algorithm using ODC (Observability Don't Care) operation to improve the power consumption of the core. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC core applied the proposed architecture is improved about 29% and dynamic power of the core using Chartered <TEX>$0.18{\mu}m$</TEX> technology library is reduced by 16%.

A scalable algorithm for RTL insertion of gated clocks based on ODCs computation

We propose a new algorithm for automatic clock-gating insertion applicable at the register transfer level (RTL). The basic rationale of our approach is to eliminate redundant computations performed by temporally unobservable blocks through aggressive exploitation of observability don't care (ODC) conditions. ODCs are efficiently detected from an RTL description by focusing only on data-path modules with easily detectable input unobservability conditions. ODCs are then propagated in the form of logic expressions toward the registers by backward traversal and levelization of the design. Finally, the logic expressions are mapped onto hardware to provide control signals to the clock-gating logic at a reduced cost in area and speed. The technique is characterized by fast processing time, high scalability to large designs, and tight user control on clock-gating overhead. Our approach is compatible with standard industrial design flows, and reduces power consumption significantly with a small overhead in delay and area. Experimental results obtained on a set of industrial RTL designs containing several tens of thousands of gates show average power reductions of around 42%. On the same examples, the application of traditional clock-gating leads to average savings reductions close to 29%.

A scalable algorithm for RTL insertion of gated clocks based on ODCs computation

We propose a new algorithm for automatic clock-gating insertion applicable at the register transfer level (RTL). The basic rationale of our approach is to eliminate redundant computations performed by temporally unobservable blocks through aggressive exploitation of observability don't care (ODC) conditions. ODCs are efficiently detected from an RTL description by focusing only on data-path modules with easily detectable input unobservability conditions. ODCs are then propagated in the form of logic expressions toward the registers by backward traversal and levelization of the design. Finally, the logic expressions are mapped onto hardware to provide control signals to the clock-gating logic at a reduced cost in area and speed. The technique is characterized by fast processing time, high scalability to large designs, and tight user control on clock-gating overhead. Our approach is compatible with standard industrial design flows, and reduces power consumption significantly with a small overhead in delay and area. Experimental results obtained on a set of industrial RTL designs containing several tens of thousands of gates show average power reductions of around 42%. On the same examples, the application of traditional clock-gating leads to average savings reductions close to 29%.