Number Of Voltage Islands Research Articles

Energy Efficiency on Multi-Core Architectures with Multiple Voltage Islands

Efficient and effective system-level power management for multi-core systems with multiple voltage islands is necessary for next-generation computing systems. This paper considers energy efficiency for such systems, in which the cores in the same voltage island have to be operated at the same supply voltage level. We explore how to map given task sets onto cores, so that each task set is assigned and executed on one core and the energy consumption is minimized. Due to the restriction to operate at the same supply voltage in a voltage island, different mappings will result in different energy consumptions. By using the simple single frequency approximation scheme (SFA) to decide the voltages and frequencies of individual voltage islands, this paper presents the approximation factor analysis (in terms of energy consumption) for simple heuristic algorithms, and develops a dynamic programming algorithm, which derives optimal mapping solutions for energy minimization when using SFA. We experimentally evaluate the running time and energy consumption performance of these algorithms on Intel's single-chip cloud computer (SCC). Moreover, we conduct simulations for hypothetical platforms with different number of voltage islands and cores per island, also considering different task partitioning policies.

Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous $V_{dd}$, $V_{th}$ Assignments, Gate Sizing, and Placement

We present a physical-synthesis based power optimization technique that simultaneously explores the four transforms, multiple Vdd, multiple Vth , cell sizing, and placement, to find a minimum power solution under timing and other constraints. The optimal selection of the design options of all transforms for all cells in the circuit is solved using a new optimization technique called discretized network flow that we have recently developed. Among the constraints we consider, timing and the voltage-island constraints are the two most important and complex ones. The voltage-island constraint specifies the maximum allowed number of voltage islands in the layout, and the requirement that each island be rectangular. We develop an approach that along with the option selection process can simultaneously determine the voltage islands needed, as well as satisfy all given constraints. Experimental results on ISCAS'89 and Faraday benchmarks show that compared to an initial wire length (WL)-optimized placement with high supply and low threshold voltage levels, we obtain a power reduction by up to 42% and an average of 30% for the same delay as that of the initial design. These improvements are also 44-50% relatively better than the improvements yielded by sequentially applying the four power reduction transforms, which is the currently standard method for applying multiple transforms. Finally, compared to an industry tool Synopsys IC Compiler (ICC) that also applies all four transforms, our method reduces power by an additional amount of up to 19%, and an average of 16%.

Energy efficient mapping and voltage islanding for regular NoC under design constraints

Computational energy consumption of the processing elements (PEs) of a NoC can be significantly reduced by scaling down their voltage levels. This creates clusters of adjacent PEs operating at the same voltage level, known as voltage islands. Excessive number of voltage islands is undesirable from the physical design perspective and due to the overhead of level shifter energy consumption between adjacent voltage islands. Considering these issues during mapping of the PEs to the NoC routers, can potentially lead to acceptable solutions with reduced overall energy consumption. In this paper, we formulate the mapping problem as an optimisation problem. We present both optimal solution, obtained by solving a mixed integer linear program (MILP), and heuristic solution based on random greedy selection. Experimental results using benchmark and real applications show that the heuristic finds near-optimal solution in almost all cases in a very small fraction of the time required to achieve the optimal solution.

Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement

High power consumption not only leads to short battery life for hand-held devices but also causes on-chip thermal and reliability problems in general. As power consumption is proportional to the square of supply voltage, reducing supply voltage can significantly reduce power consumption. Multi-supply voltage (MSV) has previously been introduced to provide finer grain power and performance tradeoff. In this paper, we propose a methodology on top of a set of algorithms to exploit nontrivial voltage island boundaries for optimal power versus design-cost tradeoff under performance requirement. Our algorithms are efficient, robust, and error-bounded and can be flexibly tuned to optimize for various design objectives (e.g., minimal power within a given number of voltage islands, or minimal fragmentation in voltage islands within a given power bound) depending on the design requirement. Our experiment on real industry designs shows a tenfold improvement of our method over current logical-boundary-based industry approach.