Number Of Unspecified Bits Research Articles

Low-power selective pattern compression for scan-based test applications

The ever-increasing test data volume and test power consumption are the two major issues in testing of digital integrated circuits. This paper presents an efficient technique to reduce test data volume and test power simultaneously. The pre-generated test sets are divided into two groups based on the number of unspecified bits in each test set. Test compression procedure is applied only to the group of test sets which contain more unspecified bits and the power reduction technique is applied to the remaining test sets. In the proposed approach, the unspecified bits in the pre-generated test sets are selectively mapped with 0s or 1s based on their effectiveness in reducing the test data volume and power consumptions. We also present a simple decoder architecture for on-chip decompression. Experimental results on ISCAS’89 benchmark circuits demonstrate the effectiveness of the proposed technique compared with other test-independent compression techniques.

Efficient Test Data Compression Achieved by Reduced Control Code

Test data compression is a major scenario in all system-on-a-chip (SOC) designs for reducing the volume of the test data. The volume of the test data directly affects the cost of SOC design. Many compression techniques have been proposed to achieve better compression. Although all the techniques proposed are applied only for those test data having larger number of unspecified bits (X's), it is not able to achieve better compression for those test data having larger number of specified values (0's and 1's). In this paper a new compression technique is proposed to achieve higher compression for test data having larger number of specified values by reducing the size of the control code. In this method the length of the control code is significantly reduced. The proposed technique is applied on ISCAS’89 benchmark circuits and its results are compared with existing method

On Test Generation With Test Vector Improvement

We investigate the introduction of a new step, referred to as test vector improvement, into test generation processes. After a fully specified test vector or a partially specified test cube t is generated at an arbitrary iteration of the test generation process, the test vector improvement step modifies t so as to increase the number of yet-undetected target faults that t detects. This is done in this paper using a simulation-based process. We show that even if t was generated using dynamic test compaction heuristics, it is possible to improve t further. When t is partially specified to accommodate test data compression, the test vector improvement step does not change the number of unspecified bits of t. The final result is a smaller test set and/or a higher fault coverage (if the test generation process does not detect all the detectable faults).

Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques

This work presents two new methods for the generation of test sets with a small number of specified bits. Such type of test sets have been proven beneficial to a large number of test-related applications such as deterministic BIST, low power testing and test set enrichment. The first technique is static, since it considers an initial test set which attempts to relax via test replacement with tests of similar coverage but with fewer specified bits. The second technique is dynamic; it generates a test set from a zero base using a hierarchical fault-compatibility algorithm. Both methods are applicable to any enumerative fault method (linear to the circuit size). The experiments performed using the stuck-at fault model demonstrate the superiority of the proposed methods over comparable existing techniques, in reducing the total number of specified bits per generated test set. The applicability of the generated relaxed test sets is demonstrated for one, out of the many, possible applications, that of deterministic test set embedding. A general framework that integrates the proposed relaxation methods in two popular LFSR-based test set embedding schemes (full and partial reseeding), along with a systematic exploration of related parameters, is proposed. The obtained results show significant reductions in seed storage requirements.

Maxx: Test Pattern Optimisation with Local Search Over an Extended Logic

In the electronic computer-aided design area, the test generation problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have some unspecified Primary Inputs (i.e. bits are assigned neither 0 nor 1). In fact, for many purposes, minimally specified tests (or patterns) are preferred. Hence, we have the test pattern optimisation (TPO) problem where the goal is to obtain a test with the maximum number of unspecified bits. In this paper we discuss different modelling approaches and present a TPO tool (Maxx) that substantially outperforms others by combining Branch-and-Bound and local search over distinct models. We apply the usual branch-and-bound search on CLP(FD) over a simple, yet incomplete, logic. A complementary Local Search is performed over an extended model, trying to improve an already computed solution by exploring an extended solution space thanks to the use of an extended logic (too complex for constraint solving). Such extended logic considers sets of dependencies on specified input values, keeping track of sources of unspecified values and their inversion parities. This allows modelling a number of alternative test vectors by unspecification of each possible input bit, thus being able to obtain an improved test vector in linear time. This paper shows, for TPO, that adapting constraint propagation with results obtained from local search outperforms the use of each of these techniques alone, obtaining significantly better results than those obtained with a highly efficient tool based on an integer linear programming formulation on a propositional satisfiability model.

An Efficient Test Relaxation Technique for Synchronous Sequential Circuits

Testing systems-on-a-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Test-set relaxation can improve the efficiency of both test compression and test compaction. In addition, the relaxation process can identify self-initializing test sequences for synchronous sequential circuits. In this paper, we propose an efficient test-relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.