Number Of Tag Bits Research Articles

Hybrid approach based on partial tag comparison technique and search methods to improve cache performance

An effective design of cache memory is an important aspect in computer architecture to improve the system performance. In this work, we study the effect of reducing the cache comparisons to map the cache address on the performance experimentally and analytically. Cache miss penalties have drastic impact on the systems’ performance. To overcome this, we propose a novel tag access scheme, which uses a partial comparison unit called n-bit comparator and use multiple search methods inside the data cache to improve the cache performance by reducing cache access time. Partial tag comparison (PTC) enables the cache to compare the tag in multi-stage techniques starting with the least significant bits (LSBs). Thus, useless tag comparison and number of tag bits being compared can be effectively reduced, hence reaching the requested tag is faster and the cache hit time is reduced. Simulation results show that the proposed approach outperforms conventional mapping techniques. The PTC technique improves the hit time in 2-bank and 4-bank fully associative caches by 70–96% and 67–88% over a cache with full tag comparison. Moreover, the proposed technique provides the minimum hit time when using a hash searching method rather than other searching methods: linear and binary.

Influence of Managing the Number of Tag Bits Transmitted on the Query Tree RFID Collision Resolution Protocol

Radio Frequency Identification (RFID) technology is increasingly becoming popular, for its widespread use and more sophisticated applications. The coexistence of tags sharing the communication channel requires solutions to message collisions, which degrade bandwidth, and increase the number of transmitted bits. A new methodology called ‘window’ is presented to manage the number of bits transmitted by a tag. The aim is show how the query tree (QT) protocol is influenced by this feature, and how the performance of the novel protocol, query window tree (QwT), improves when the tag ID distribution is correlated. Therefore, we have performed a fair comparison of the Query Tree and the new proposed QwT protocol for various tag ID distributions. Simulations show that the QwT positively decreases the total number of bits that are transmitted by tags.

Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching

We propose a novel energy-efficient cache architecture based on a matching mechanism that uses a reduced number of tag bits. The idea behind the proposed architecture is based on moving a large subset of the tag bits from the cache into an external register (called the Tag Overflow Buffer) that serves as an identifier of the current locality of the memory references. Dynamic energy efficiency is achieved by accessing, for most of the memory references, a reduced-tag cache; furthermore, because of the reduced number of tag bits, leakage energy is also reduced as a by-product. We achieve average energy savings ranging from 16% to 40% (depending on different cache structural parameters) on total (i.e., static and dynamic) cache energy, and measured on a standard suite of embedded applications.

Tag Compression for Low Power in Dynamically Customizable Embedded Processors

We present a methodology for power reduction by instruction/data cache-tag compression for low-power embedded processors. By statically analyzing the code/data memory layouts for the application hot spots, a variety of proposed schemes for effective tag-size reduction can be employed for power minimization in instruction and data caches. The schemes rely on significantly reducing the number of tag bits stored in the tag arrays for cache-conflict identification, thus considerably decreasing the number of active bitlines, sense amps, and comparator cells. We present a set of tag compression techniques and evaluate each of them separately in terms of efficiency and required hardware support. A detailed very large scale integrated implementation has been performed and a number of experimental results on a set of embedded applications is reported for each technique. Energy dissipation decreases of up to 95% can be observed for the tag arrays, implying significant energy reductions in the range of 50% when amortized across the overall cache subsystem.

Partial resolution in branch target buffers

Branch target buffers, or BTBs, are small caches for program branching information. Like data caches, addresses are divided into equivalence classes based on their low order bits. Unlike data caches, however, complete resolution of a single address from within an equivalence class is not required for correct execution. Substantial savings are therefore possible by employing partial resolution, using fewer tag bits than necessary to uniquely identify an address. We present the relationship between the number of tag bits in a branch target buffer and prediction accuracy, based on dynamic simulations of the SPECINT92 benchmark suite. For a 512 entry BTB, on average only two tag bits are necessary to obtain 99.9 percent of the accuracy obtainable with a full tag; no more than nine tag bits are required to obtain identical prediction accuracy. This suggests that microprocessors can achieve substantial area savings in their BTB tag stores by employing partial resolution.