Number Of Switching Stages Research Articles

Wavelength-division-multiplexing optical Benes-type networks with simultaneous space-wavelength switching

We propose new wavelength-division-multiplexing (WDM) optical interconnect architectures with simultaneous space-wavelength switching capability and reduced complexity. The proposed architectures improve over existing space-wavelength Benes networks, as these require the same number of stages and hardware components as a pure space Benes network. In addition, wavelength conversion in the proposed designs occurs only between two predefined wavelengths, eliminating the need for expensive wide-range wavelength converters used in most existing designs. We develop and characterize three families of WDM Benes networks with reduced complexity, and we present a typical architecture in each of the families. We also propose a routing strategy to establish connections over each of the proposed families. Finally, we present a comparative analysis of the properties of proposed architectures with respect to known WDM Benes networks. It is shown that the new designs require a smaller number of switching stages and space switches, and they have a smaller overall cost compared to most existing WDM Benes interconnects.

Rerouting network: a high-performance self-routing switch for B-ISDN

A high-performance self-routing switch is proposed for ATM (asynchronous transfer mode) switch systems. Switching performance is enhanced by a rerouting algorithm applied to a particular multistage interconnection algorithm. The interconnection algorithm offers many access points to the output and resolves output contention by layering buffers at each switching stage. The author analyzes switching performance and shows that this switch can be easily engineered to have high throughput and low cell loss probability by increasing the number of switching stages. The author also illustrates that the number of switching stages required for a given cell loss probability shows gradual growth with increasing switch size. Analysis shows that the proposed switch is robust even with respect to nonuniform traffic. >

The PM221 interconnection network

A scheme based on the standard multiplier recoding technique that enables the use of (5*5) switches for PM2I networks is presented. The connections between switching stages are based on the modified PM2I functions, and are called plus-minus-2/sup 2i/ (PM22I); hence, these networks are called the PM22I networks. Since the number of switching stages in the PM22I networks is one-half of those in the PM2I networks, with a moderate increase in the switch size from (3*3) to (5*5), these networks provide similar design tradeoffs availability by the (2*2) and (4*4) cube networks. >

The virtual path identifier and its applications for routeing and priority of connectionless and connection‐orientated services

AbstractA feature of ATM networks is that they can be configured with paths routed through a number of switching stages which can each take many thousands of connections and which can each be assigned capacity dynamically. A large number of such paths, known as virtual paths, can be established from each network node without consuming much network capacity, since they can be assigned limited or zero capacity when unused. Virtual paths can be used to provide faster connection set‐up times or a faster transfer time for connectionless messages, and greater routeing flexibility. In particular they can be used to provide very fast transfer of signalling information between any two processors in a set of many thousands configured as a distributed processing control plane. They can also be used to indicate quality of service (QOS) values. These different issues are discussed in this paper, leading to some recommendations on the size of the virtual path identifier (VPI) field suitable for signalling and connectionless and connection‐orientated services.

On Nonblocking Switching Networks Composed of Digital Symmetrical Matrices

Significant advances in semiconductor technology make it possible to construct new components called digital symmetrical matrices, which mix in the same integrated circuit, time and space switching. In this paper, structures of multistage nonblocking networks composed of such matrices are described. The condition under which the network will be nonblocking is formulated, and the relationship between the maximal capacity of the network and the number of switching stages is discussed. Formulas for designing optimal threeand five-stage networks are derived. It is shown that general multistage networks should have as few stages as possible for minimizing the cost.