Number Of Processor Cores Research Articles

An Algorithm for Solving the Problem of Phase Unwrapping in Remote Sensing Radars and Its Implementation on Multicore Processors

The problem of the interferometric phase unwrapping in radar remote sensing of Earth systems is considered. Such interferograms are widely used in the problems of creating and updating maps of the relief of the Earth’s surface in geodesy, cartography, environmental monitoring, geological, hydrological and glaciological studies, and for monitoring transport communications. Modern radar systems have ultra-high spatial resolution and a wide band, which leads to the need to unwrap large interferograms from several tens of millions of elements. The implementation of calculations by these methods requires a processing time of several days. In this paper, an effective method for equalizing the inverse vortex field for phase unwrapping is proposed, which allows solving a problem with quasi-linear computational complexity depending on the interferogram size and the number of singular points on it. To implement the method, a parallel algorithm for solving the problem on a multi-core processor using OpenMP technology was developed. Numerical experiments on radar data models were carried out to investigate the effectiveness of the algorithm depending on the size of the source data, the density of singular points and the number of processor cores.

Determining the relationship between the simulation duration by the discrete element method and the computer system technical characteristics

The object of this study is the relationship between the technical characteristics of a computing system and the duration of modeling the motion of particles of granular materials by the discrete element method. The scheme of the calculation algorithm is presented; its main stages are analyzed. A 3D model of a belt feeder and a mathematical model of particle motion were developed for calculations by the discrete element method in the EDEM 2017 environment. The physical and mechanical properties of bulk material are defined; the structural and technological parameters of equipment are determined. The parameters of the algorithm and computing system are analyzed. Those parameters are defined, the change of which does not affect the accuracy of calculations but can change the volume of computing resources used. These include the number of particles of loose material, the «grid» step, and the number of processor cores. The influence of these parameters on the duration of simulation was determined using a complete factor experiment. Experimental studies have shown that for the duration of the simulation, the determining parameters are the number of particles and the number of processor cores. It was established that there is a linear relationship between the duration of the simulation and the number of particles. The regression equation is built, which makes it possible to predict the simulation time. It was also established that the software does not fully use all available computing resources; the maximum load on the processor when utilizing all available cores is 57 %. The use of RAM and disk subsystem almost did not change during simulation. The results reported here make it possible to plan the use of computing resources for research using the discrete element method and to predict the simulation time

Towards automatic finite-element methods for geodynamics via Firedrake

Abstract. Firedrake is an automated system for solving partial differential equations using the finite-element method. By applying sophisticated performance optimisations through automatic code-generation techniques, it provides a means of creating accurate, efficient, flexible, easily extensible, scalable, transparent and reproducible research software that is ideally suited to simulating a wide range of problems in geophysical fluid dynamics. Here, we demonstrate the applicability of Firedrake for geodynamical simulation, with a focus on mantle dynamics. The accuracy and efficiency of the approach are confirmed via comparisons against a suite of analytical and benchmark cases of systematically increasing complexity, whilst parallel scalability is demonstrated up to 12 288 compute cores, where the problem size and the number of processing cores are simultaneously increased. In addition, Firedrake's flexibility is highlighted via straightforward application to different physical (e.g. complex non-linear rheologies, compressibility) and geometrical (2-D and 3-D Cartesian and spherical domains) scenarios. Finally, a representative simulation of global mantle convection is examined, which incorporates 230 Myr of plate motion history as a kinematic surface boundary condition, confirming Firedrake's suitability for addressing research problems at the frontiers of global mantle dynamics research.

Active Ultrahigh-Q (0.2 × 106 ) THz Topological Cavities on a Chip.

Rapid scaling of semiconductor devices has led to an increase in the number of processor cores and integrated functionalities onto a single chip to support the growing demands of high-speed and large-volume consumer electronics. To meet this burgeoning demand, an improved interconnect capacity in terms of bandwidth density and active tunability is required for enhanced throughput and energy efficiency. Low-loss terahertz silicon interconnects with larger bandwidth offer a solution for the existing inter-/intrachip bandwidth density and energy-efficiency bottleneck. Here, a low-loss terahertz topological interconnect-cavity system is presented that can actively route signals through sharp bends, by critically coupling to a topological cavity with an ultrahigh-quality (Q) factor of 0.2 × 106 . The topologically protected large Q factor cavity enables energy-efficient optical control showing 60dB modulation. Dynamic control is further demonstrated of the critical coupling between the topological interconnect-cavity for on-chip active tailoring of the cavity resonance linewidth, frequency, and modulation through complete suppression of the back reflection. The silicon topological cavity is complementary metal-oxide-semiconductor (CMOS)-compatible and highly desirable for hybrid electronic-photonic technologies for sixth (6G) generation terahertz communication devices. Ultrahigh-Q cavity also paves the path for designing ultrasensitive topological sensors, terahertz topological integrated circuits, and nonlinear topological photonic devices.

A parallel scalable domain decomposition preconditioner for elastic crack simulation using XFEM

AbstractIn this article, a parallel overlapping domain decomposition preconditioner is proposed to solve the linear system of equations arising from the extended finite element discretization of elastic crack problems. The algorithm partitions the computational mesh into two types of subdomains: the regular subdomains and the crack tip subdomains based on the observation that the crack tips have a significant impact on the convergence of the iterative method while the impact of the crack lines is not that different from those of regular mesh points. The tip subdomains consist of mesh points at crack tips and all neighboring points where the branch enrichment functions are applied. The regular subdomains consist of all other mesh points, including those on the crack lines. To overcome the mismatch between the number of subdomains and the number of processor cores, the proposed method is divided into two steps: solve the crack tip problem and then the regular subdomain problem during each iteration. The proposed method was used to develop a parallel XFEM package which is able to test different types of iterative methods. To achieve good parallel efficiency, additional methods were introduced to reduce communication and to maintain the load balance between processors. Numerical experiments indicate that the proposed method significantly reduces the number of iterations and the total computation time compared to the classical methods. In addition, the method scales up to 8192 processor cores with over 70% parallel efficiency to solve problems with more than degrees of freedom.

Improved Scheduling Algorithm for Synchronous Data Flow Graphs on a Homogeneous Multi-Core Systems

In order to accelerate the execution of streaming applications on multi-core systems, this article studies the scheduling problem of synchronous data flow graphs (SDFG) on homogeneous multi-core systems. To describe the data flow computation process, we propose the SDAG (Super DAG) computation model based on the DAG model combined with data-driven thoughts. Further, we analyze the current common SDFG scheduling algorithms and propose an improved SDFG scheduling algorithm, LSEFT (level-shortest-first-earliest-finish time). The LSEFT algorithm uses an inverse traversal algorithm to calculate the priority of tasks in the task-selection phase; the shortest-job-priority earliest-finish-time policy is used in the processor selection phase to replace the original long job priority policy. In the experimental part, we designed an SDFG random generator and generated 958 SDFGs with the help of the random generator as test cases to verify the scheduling algorithm. The experimental results show that our improved algorithm performs well for different numbers of processor cores, especially for 8 cores, where the speedup of our improved algorithm improves by 10.17% on average.

Performance and programmability comparison of the thick control flow architecture and current multicore processors

Commercial multicore central processing units (CPU) integrate a number of processor cores on a single chip to support parallel execution of computational tasks. Multicore CPUs can possibly improve performance over single cores for independent parallel tasks nearly linearly as long as sufficient bandwidth is available. Ideal speedup is, however, difficult to achieve when dense intercommunication between the cores or complex memory access patterns is required. This is caused by expensive synchronization and thread switching, and insufficient latency toleration. These facts guide programmers away from straight-forward parallel processing patterns toward complex and error-prone programming techniques. To address these problems, we have introduced the Thick control flow (TCF) Processor Architecture. TCF is an abstraction of parallel computation that combines self-similar threads into computational entities. In this paper, we compare the performance and programmability of an entry-level TCF processor and two Intel Skylake multicore CPUs on commonly used parallel kernels to find out how well our architecture solves these issues that greatly reduce the productivity of parallel software development. Code examples are given and programming experiences recorded.

A novel MPI+MPI hybrid approach combining MPI-3 shared memory windows and C11/C++11 memory model

The increase of the number of cores in processors used in modern cluster architectures advocates hybrid parallel programming, combining Message Passing Interface (MPI) for internode operations and a shared memory treatment of intranode operations. We propose an MPI+MPI hybrid approach to parallel programming in which shared memory operations are managed by the combination of MPI shared memory windows introduced with MPI-3, C11/C++11 atomic operations and the associated multi-thread memory model. We illustrate the method on fundamental parallel operations (barrier, reduction) and on the ghost update, which is prevalent in many parallel numerical methods. The performance tests on Reedbush-U and Oakbridge-CX systems show that using the C11/C++11 memory model to manage shared memory windows can achieve levels of performance comparable to state of the art MPI implementations, while reducing the variance of execution times as well as increasing the level of synchronization between processes, especially in multiple nodes environments. It also reduces significantly the execution time of ghost updates compared to flat MPI, and the synchronization of shared data with the C++11 memory model is observed to be more efficient than other synchronization methods based on RMA utilities.

Cost-efficient reconfigurable geometrical bus interconnection system for many-core platforms

System-on-chip (SoC) embedded computing platforms can support a wide range of next generation embedded artificial intelligence and other computationally intensive applications. These platforms require cost effective interconnection network. Network-on-chip has been widely used today for on-chip interconnection. However, it is still considered expensive for large system sizes. As full bus-based interconnection has high number of bus connections, reduced bus connections might offer considerable implementation economies with relatively small design cost for field programmable gate arrays (FPGAs) based embedded platforms. In this paper, we propose a cost efficient generalized reconfigurable bus-based interconnection for many-core system with reduced number of bus connections. We generalize the system with b =min {n,m}/k number of interconnect buses in which where n is the number of processor cores, m is the number of memory-modules and k is the general bus reduction factor. We present four geometrical interconnect configurations and provide their characterization in terms of memory bandwidth, cost per bandwidth and bus fault tolerance for various system sizes. Our results show that these configurations provide reduced cost per bandwidth and can achieve higher system throughput with bus cache.

Multilevel space‐time multiplicative Schwarz preconditioner for parabolic equations

AbstractSpace‐time methods are able to solve time‐dependent problems faster by exploiting the full power of high‐performance computer. In this article, a multilevel space‐time multiplicative Schwarz method is presented for solving parabolic equations in parallel on both spatial and temporal directions. In the implementation, the proposed Schwarz method is treated as preconditioner for GMRES, that is, a coupled system arising from the discretization of the parabolic equation is solved by using a multiplicative Schwarz preconditioned GMRES algorithm. We develop an optimal convergence theory to show that the convergence rate is bounded and independent of the spatial mesh sizes, the time step size, the number of subdomains, the number of levels, and the window size. Some numerical results obtained on a parallel computer with thousands of processors are presented to confirm the theory in terms of optimality and scalability. Moreover, numerical comparisons with traditional time‐stepping algorithms show that the proposed space‐time method earns lots of benefits when the number of processor cores is large.

Implementation of a high-accuracy phase unwrapping algorithm using parallel-hybrid programming approach for displacement sensing using self-mixing interferometry

Phase unwrapping is an integral part of multiple algorithms with diverse applications. Detailed phase unwrapping is also necessary for achieving high-accuracy metric sensing using laser feedback-based self-mixing interferometry (SMI). Among SMI specific phase unwrapping approaches, a technique called Improved Phase Unwrapping Method (IPUM) provides the highest accuracy. However, due to its complex, sequential, and compute-intensive nature, this method requires a high-performance computing architecture, capable of scalable parallel processing so that such a high-accuracy algorithm can be used for high-bandwidth sensing applications. In this work, the existing sequential IPUM C program is parallelized by using hybrid OpenMP/MPI (Open Multi-Processing/Message Passing Interface) parallel programming models and tested on Barcelona Supercomputing Center Nord-III Supercomputer. The computational performance of the proposed parallel-hybrid IPUM algorithm is compared with existing IPUM sequential code by executing multi-core and uni-core processor architecture, respectively. While comparing the performance of sequential IPUM with the parallel-hybrid IPUM algorithm on 16 nodes of Nord-III supercomputer, the results show that the parallel-hybrid algorithm gets 345.9x times performance improvement as compared to IPUM’s standard, sequential implementation on a single node system. The results show that the parallel-hybrid version of IPUM gives a scalable performance for different target velocities and a different number of processing cores.

DiRong1.0: a distributed implementation for improving routing network generation in model coupling

Abstract. A fundamental functionality of model coupling in an Earth system model is to efficiently handle data transfer between component models. An approach of M×N communication following a routing network has been used widely used for data transfer, and routing network generation becomes a major step required to initialize data transfer functionality. Some existing coupling software such as the Model Coupling Toolkit (MCT) and the existing versions of the Community Coupler (C-Coupler) employ a global implementation of routing network generation that relies on gather–broadcast communications, which can be very inefficient under a case of a large number of processes. This is an important reason why the initialization cost of a coupler increases with the number of processor cores. In this paper, we propose a “distributed implementation for routing network generation, version 1.0” (DiRong1.0), which does not introduce any gather–broadcast communication. Empirical evaluations show that DiRong1.0 is much more efficient than the global implementation. DiRong1.0 has already been implemented in C-Coupler2, and we believe that some other couplers can also benefit from it.

More bang for your buck: Boosting performance with capped power consumption

Achieving faster performance without increasing power and energy consumption for computing systems is an outstanding challenge. This paper develops a novel resource allocation scheme for memory-bound applications running on High-Performance Computing (HPC) clusters, aiming to improve application performance without breaching peak power constraints and total energy consumption. Our scheme estimates how the number of processor cores and CPU frequency setting affects the application performance. It then uses the estimate to provide additional compute nodes to memory-bound applications if it is profitable to do so. We implement and apply our algorithm to 12 representative benchmarks from the NAS parallel benchmark and HPC Challenge (HPCC) benchmark suites and evaluate it on a representative HPC cluster. Experimental results show that our approach can effectively mitigate memory contention to improve application performance, and it achieves this without significantly increasing the peak power and overall energy consumption. Our approach obtains on average 12.69% performance improvement over the default resource allocation strategy, but uses 7.06% less total power, which translates into 17.77% energy savings.

Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning

As the number of processing cores and associated threads in chip multiprocessors (CMPs) continues to scale out, on-chip memory access latency dominates application execution time due to increased data movement. Although tiled CMP architectures with distributed shared caches provide a scalable design, increased physical distance between requesting and responding cores has led to both increased on-chip memory access latency and excess energy consumption. Near data processing is a promising approach that can migrate threads closer to data, however prior hand-engineered rules for fine-grained hardware-level thread migration are either too slow to react to changes in data access patterns, or unable to exploit the large variety of data access patterns. In this article, we propose to use reinforcement learning (RL) to learn relatively complex data access patterns to improve on hardware-level thread migration techniques. By utilizing the recent history of memory access locations as input, each thread learns to recognize the relationship between prior access patterns and future memory access locations. This leads to the unique ability of the proposed technique to make fewer, more effective migrations to intermediate cores that minimize the distance to multiple distinct memory access locations. By allowing a low-overhead RL agent to learn a policy from real interaction with parallel programming benchmarks in a parallel simulator, we show that a migration policy which recognizes more complex data access patterns can be learned. The proposed approach reduces on-chip data movement and energy consumption by an average of 41%, while reducing execution time by 43% when compared to a simple baseline with no thread migration; furthermore, energy consumption and execution time are reduced by an additional 10% when compared to a hand-engineered fine-grained migration policy.

Improving the performance of fragments of computer code with high time costs based on parallel programming technologies

This article describes the process of converting the program from single-threaded to multithreaded mode. The influence of the number of threads of execution on the total execution time of the code. The problem of spending much time to run programs solved by incremental parallelization when the code is designed for sequential execution, are added to the parallelizing directives. Are similar libraries for working with threads in other programming languages and the advantages of OpenMP over other libraries. Considered a model of parallelizing OpenMP directives, which is time-consuming to run the snippet in multi-threaded mode. The article also presents example code implemented using the C++ language, which built the parallelizing directives of OpenMP. In this model, the estimated execution time of a code snippet of a program with different number of threads. The study showed that with increasing the number of threads the run time is significantly reduced on the average in 1,5–2 times. This happens until the moment when the number of threads will be equal to the number of processor cores. If the number of threads becomes greater than the number of processor cores, the execution time of the program remains virtually unchanged. Are the OpenMP library allows to significantly shorten the program, which can be critical for works of real-time systems, to reduce the time of creating multithreaded applications is simple inserts directives of the library, to reduce the number of errors made by the programmer in the course of working with multi-threaded applications.

Neutron transport criticality calculations using a parallel monolithic multilevel Schwarz preconditioner together with a nonlinear diffusion acceleration method

The multigroup neutron transport criticality calculations using modern supercomputers have been widely employed in a nuclear reactor analysis for studying whether or not a system is self-sustaining. However, the design and development of efficient parallel algorithms for the transport criticality calculations is challenging especially when the number of processor cores is large and an unstructured mesh is adopted. In particular, both the compute time and the memory usage have to be carefully taken into consideration due to the dimensionality of the neutron transport equations. In this paper, we study a monolithic multilevel Schwarz preconditioner for the transport criticality calculations based on a nonlinear diffusion acceleration (NDA) method. In NDA, the multigroup nonlinear diffusion equations are computed using an inexact Jacobian-free Newton method with an initial guess generated from a few inverse power iterations. The computed scalar fluxes and eigenvalue are used to evaluate the fission and scattering terms of the transport equations, and then the nonlinear system of transport equations is simplified to a linear system of equations. The linear systems of equations arising from the discretizations of the nonlinear diffusion equations and the transport equations need to be efficiently solved. We propose a monolithic multilevel Schwarz method that is capable of efficiently handling the systems of linear equations for both the transport system and the diffusion system. However, in the multilevel method, algebraically constructing coarse spaces is expensive and often unscalable. We study a subspace-based coarsening algorithm to address such a challenge by exploring the matrix structures of the transport equations and the nonlinear diffusion equations. We numerically demonstrate that the monolithic multilevel preconditioner with the subspace-based coarsening algorithm is twice as fast as that equipped with an unmodified coarsening approach on thousands of processor cores for an unstructured mesh neutron transport problem with billions of unknowns.

Выбор оптимального количества процессорных ядер для алгоритма многократной маркировки перколяционных кластеров на высокопроизводительных вычислительных системах

The article is about the research of a optimum number of processor cores for launching the Parallel Cluster Multiple Labeling Technique on modern supercomputer systems installed in the JSCC RAS. This technique may be used in any field as a tool for differentiating large lattice clusters, because it is given input in a format independent of the application. At the JSCC RAS, this tool was used to study the problem of the spread of epidemics, for which an appropriate multiagent model was developed. In the course of imitation experiments, a variant of the Parallel Cluster Multiple Labeling Technique for percolation Hoshen-Kopelman clusters related to the tag linking mechanism, which can also be used in any area as a tool for differentiating large-size lattice clusters, was used to be improved on a multiprocessor system.

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets

High Level Synthesis (HLS) tools targeting Field Programmable Gate Arrays (FPGAs) aim to provide a method for programming these devices via high-level abstractions. Initially, HLS support for FPGAs focused on compiling C/C++ to hardware circuits. This raised the issue of determining the programming practices which resulted in the best performing circuits. Recently, to further increase the applicability of HLS approaches, renewed effort was placed on support for HLS of OpenCL code for FPGA, raising the same issues of coding practices and performance portability. This paper explores the performance of OpenCL code compiled for FPGAs for different coding techniques. We evaluate the use of task-kernels versus NDRange kernels, data vectorization, the use of on-chip local memories, and data transfer optimizations by exploiting burst access inference. We present this exploration via a case study of the k-means algorithm, and produce a total of 10 OpenCL implementations of the kernel. To determine the effects of different data set characteristics, and to determine the gains from specialization based on number of attributes, we generated a total of 12 integer data sets. The data sets vary regarding the number of instances, number of attributes (i.e., features), and number of clusters. We also vary the number of processing cores, and present the resulting required resources and operating frequencies. Finally, we execute the same OpenCL code on a 4 GHz Intel i7-6700K CPU, showing that the FPGA achieves speedups up to $1.54 {\times } $ for four cases, and energy savings up to 80% in all cases.

Big Data Analytics for Diabetes Prediction on Apache Spark

Dangerous diseases like diabetes, in which blood glucose levels are too high, some machine learning models have been used to classify or predict the patient state. Currently, the collected dataset size increases dramatically. Therefore, big data analytics technology is an essential factor in building an efficient healthcare system that can fit for the future. This paper discusses the effect of using big data analytics with different dataset sizes by usinga different number of processing cores over apache spark. The system has been evaluated using several performance evaluation metrics like accuracy, recall, precision, time, etc. A comparative study made among various algorithms such as Support Vector Machine (SVM), Naive Bayes (NB), Decision Tree (DT), and Random Forest (RF). The experimental result shows that the most accurate models were when using RF, and SVM, and the minimum time model was when using NB algorithm.

Stochastic multi-objective Pareto-optimization framework for fully automated ab initio network-on-chip design

Abstract With the advent of multi-core processors, network-on-chip design has been crucial in addressing network performances, such as bandwidth, power consumption, and communication delays when dealing with on-chip communication between the increasing number of processor cores. As the numbers of cores increase, network design becomes inherently more complex. Therefore, there is a critical need in soliciting computer aid in determining network configurations that afford optimal performance given multi-objectives, such as resource and design constraints. We have devised a stochastic multi-objective Pareto-optimization framework that fully automatically explores the space of possible network configurations to determine optimal network latencies, power consumption, and the corresponding link allocations, i.e., the actual network-on-chip design, ab initio with only the number of routers given. For a given number of routers, average network latency and power consumption as example performance objectives can be displayed in form of Pareto-optimal fronts, thus not only offering a powerful automatic network-on-chip design tool, but also affording trade-off studies for the chip designers.