Number Of Parity Check Bits Research Articles

A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes

The use of error-correcting codes is a common strategy to protect memories from errors. Single-error correction, double-error detection linear block codes have been traditionally utilized. However, there are applications where multiple errors are frequent and more complex codes are needed. Orthogonal Latin square codes are one type of codes with multiple-error-correction capability. They are of interest for memory protection because they can be decoded with low complexity and delay. This paper presents a modification to orthogonal Latin square codes that reduces the number of parity check bits to be stored in memory therefore lowering the memory overhead needed to implement the codes. The proposed codes can also be decoded with low delay and complexity. This paper also presents an evaluation of the encoder and decoder implementations for various word sizes and compares them with the standard orthogonal Latin square implementations. The results show that they are similar in terms of circuit area and introduce only a small penalty in delay.

Neutron Radiation Induced Soft Error Rates for an Adjacent-ECC Protected SRAM in 28 nm CMOS

We report on measured neutron radiation induced soft error rates (SER) for an academic, full-custom, low-power 75 kb SRAM macro in a commercial 28 nm CMOS process protected with an adjacent-bit error correction circuit (ECC). In low voltage (0.5 V) power saving mode, measurements show an 189x improvement in SER over an unprotected baseline array and a 5x improvement over a traditional single-error-correcting-double-error-detecting (SEC-DED) code using the same number of parity check-bits. Further, simulation results show an over 2x reduction in SER compared to other multi-bit ECCs while using three fewer check-bits. Chip measurement results show that the low voltage retention mode provides a 89.7% reduction in cell leakage current/bit compared to the nominal supply voltage. All radiation measurement data has been collected at the TRIUMF Neutron Irradiation Facility in Vancouver, Canada.