Number Of Output Voltage Levels Research Articles

Circulating current suppression and natural voltage balancing using phase-shifted modulation for modular multilevel converter

The challenge of achieving a balanced capacitor voltage is one of the factors affecting the efficient operation of modular multilevel converters (MMC). This paper investigates this challenge through a proposed method that utilizes a high carrier frequency phase-shifted pulse width modulation (PS-PWM) scheme. This method aims to achieve natural balancing without the need for any additional control mechanisms. Moreover, the number of output voltage levels is affected by the phase shift between the carriers of the upper and lower arms. When there is no phase shift, N<sup>+1</sup> discrete levels are achieved, but when there is a phase shift, the number of discrete levels increases to 2<sup>N+1</sup>. The proportional-resonant (PR) controller and moving average filter (MAF) are employed to decrease the capacitor voltage ripples by suppressing the fourth and second harmonics in the circulating currents. The MMC inverter structure is modeled and simulated in the PLECS and MATLAB/Simulink environments to evaluate the impact of this control scheme on the converter’s performance.

A five‐level common‐ground inverter with step‐up/step‐down dual‐mode operation for transformerless grid‐connected PV application

AbstractStep‐up multilevel inverters with common‐ground feature are attractive for transformerless photovoltaic systems. However, their performance deteriorates at step‐down voltage range. Considering a five‐level inverter with double voltage gain, the number of output voltage levels decreases from 5 to 3 for a modulation index smaller than 0.5, declining the quality of the output currents. This paper proposes a new dual‐mode five‐level common‐grounded inverter with a reduced number of switches. The proposed topology has the ability to operate as step‐up or step‐down making it well suited for application with wide input voltage range. The proposed inverter consists of five unidirectional switches, one bidirectional switch, two diodes, and two capacitors. In addition, the description of the topology, the design guidelines, and a comparison among the main topologies are given in detail. Experimental results are obtained to attest the practicability of the proposed solution.

Performance Analysis of Harmonic-Reduced Modified PUC Multi-Level Inverter Based on an MPC Algorithm

Renewable and distributed energy generation includes wind turbines, fuel cells, solar cells, and batteries. These distributed energy sources need special power converters in order to connect them to the grid and make the generated power available for public use. Solar energy is the most readily available energy source; hence, if utilized properly, it can power up both domestic and industrial loads. Solar cells produce DC power, and this should be converted to an AC source with the help of inverters. A multi-level inverter for an application is selected based on a trade-off between cost, complexity, losses, and total harmonic distortion (THD). A packed U-cell (PUC) topology is composed of power switches and voltage sources connected in a series-parallel fashion. This basic unit can be extended to a greater number of output voltage levels. The significance of this design is the reduced use of power switches, gate drivers, protection circuits, and capacitors. The converter presented in this paper is a 31-level topology switched by a variable switching frequency-based model predictive controller that helps in achieving optimal output with reduced harmonics to a great extent. The gate driver circuit is also optimized in terms of power consumption and size complexity. A comparison of the 9-level and the 31-level PUC inverters is carried out to study the impact of the number of levels on the total harmonic distortion. The simulation results depict that the total harmonic distortion (THD) for a nominal modulation index of 0.8 is 11.54% and 3.27% for the 9-level multi-level inverter (MLI) and the 31-level modified packed U-cell multi-level inverter (MPUC-MLI), respectively. The reduction in THD is attributed to the increased number of steps in the output when using the model predictive controller.

A new symmetric modular eleven‐level inverter using single and double source unit for low voltage applications with reduced number of switches

AbstractThis study proposes a modular multilevel inverter for low‐voltage applications, including ac‐coupled renewables and energy storage systems. These inverters require many switches and gate drivers in their structures, which complicates the control system, reduces efficiency, and increases costs. This study introduces a new modular multilevel inverter that can produce five levels of positive voltage using only six power switches and five DC voltage sources. The basic unit is composed of a single‐ and double‐source (SDS) unit. SDS reduces the number of power electronic components, such as the insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocking voltage by switches. The proposed topology can boost the number of output voltage levels and decrease the number of switching devices and voltage stress using some combinations of basic submodules. The performance of the proposed 11‐level single‐phase inverter is compared with that of the conventional structures and recent symmetric topologies considering the number of switches, cost, and efficiency. The waveform quality and both the voltage and current harmonic characteristics were determined in accordance with IEEE 519–2014. Finally, an 11‐level prototype was constructed to validate the theoretical analysis, feasibility, and effectiveness of the proposed inverter.

A variable frequency injection method for modular multilevel converters in variable speed drives

Modular multilevel converter (MMC) is a novel circuit that has appeared in the last few decades, and has been extensively applied to medium/high voltage scenarios, especially in motor drive owing to its scalability and easy to supply a higher number of output voltage levels. As theoretical analysis shows, the sub-module (SM) capacitor voltage magnitude is positively related to the converter output current amplitude and conversely connected to the fundamental frequency. Therefore, the prime challenge of applying MMC to variable speed drives is that there is a huge voltage oscillation in SM capacitor voltage during low-speed working. An innovative high-frequency voltage injection modality to diminish the fluctuation of the capacitor voltage in variable speed drives is proposed in this paper, in which the frequency of the injected component can be changed with the operating frequency of the converter and the low frequency component of power can be converted into high frequency component. The discussed measure not only significantly reduces the voltage float in capacitor, but also avoids the overmodulation of arm voltage modulation waveform caused by high frequency of injection component when converter works in low frequency. With the improved method, the performance of motor at low frequency is enhanced. Finally, the feasibility and effectiveness of the proposed improved high-frequency voltage injection method are verified by simulation and experiment.

A Novel Multilevel Inverter With Self-Balancing Capability of Capacitors Voltage; Structure, Modulation, and Operation

This article presents a 17-level asymmetrical multilevel inverter (MLI) with a reduced number of components. This structure can also be used symmetrically to increase redundancy. It can be extended in a modular fashion to increase the number of output voltage levels. Moreover, the capacitor voltages are self-balanced and do not require a sensor to stabilize the voltage. Due to the application of a level-shifted modulation (LSM), most power switches are turned on and off at low and fundamental frequencies, which will significantly reduce losses. Other benefits of this topology are the inherent production of negative levels without H-bridge, reduced total standing voltage (TSV), and low total harmonic distortion (THD). Power loss analysis is also presented as well as calculation of capacitances. MATLAB simulation results and laboratory implementation are carried out to evaluate circuit performance in different operational conditions.

HERIC-Clamped and PN-NPC Inverters With Five-Level Output Voltage and Reduced Grid-Interfaced Filter Size

Transformerless grid-connected inverters with highly efficient and reliable inverter concept (HERIC) and positive-negative neutral point-clamped (PN-NPC) circuit configurations exhibit excellent performance in terms of overall efficiency, common-mode voltage, and alleviated leakage current concern. These inverters are designed to generate only a three-level (3 L) output voltage waveform, thereby reducing the power density of a conversion system. On the other hand, it is well-known that increasing the inverter output voltage levels entails the reduction of the output filter size. In this regard, this article aims to develop a five-level (5 L) inverter output voltage for the improved versions of HERIC-clamped and original PN-NPC inverters. This is achieved with either phase-shifted or level-shifted pulse width modulation technique leading to further quality improvement of ac voltage and current waveforms through increasing the number of output voltage levels. Therefore, a much smaller output filter size can be utilized, while the overall efficiency of the entire system is enhanced. Two laboratory-built SiC-based prototypes for both the proposed HERIC-clamped (1.8 kW) and PN-NPC-5 L (2 kW) inverters have been fabricated to show the feasibility and effectiveness of the proposed solution via experiments.

Improved Seven-Level Multilevel DC-Link Inverter with Novel Carrier PWM Technique

Multilevel inverters have emerged as a viable alternative for various power electronic applications. It offers significant features in terms of reduced total harmonic distortion (THD) due to more number of output voltage levels, lower filter size, and voltage stress and reduced switching losses when compared to conventional two-level inverters. The classical topologies such as neutral point clamped, flying capacitor and cascaded H-bridge (CHB) are very popular for industrial applications. All these topologies have limitations in terms of more component count, capacitor voltage balancing for increased number of voltage levels. In this regard, multi-level DC link (MLDCL) inverter has been introduced as an improvement with respect to CHB MLI in terms of reduced switch count and is considered here for the study. This paper presents a single-phase MLDC link inverter with a modified carrier-based level-shifted phase disposition sinusoidal pulse width modulation (LS-PD-SPWM) technique. The proposed novel carrier PWM is compared with the conventional modulation techniques in terms of THD. The performance of the proposed modulation technique is analyzed through simulation studies in MATLAB software. A laboratory prototype model is developed in order to validate the experimental results.

Switched-Capacitor Multilevel Inverters: A Comprehensive Review

Multilevel inverters (MLIs) with switched-capacitor (SC) units have been a widely rehearsed research topic in power electronics since the last decade. Inductorless/transformerless operation with voltage-boosting feature and inherent capacitor self-voltage balancing performance with a reduced electromagnetic interference make the SC-MLI an attractive converter over the other available counterparts for various applications. There have been many developed SC-MLI structures recently put forward, where different basic switching techniques are used to generate multiple (discrete) output voltage levels. In general, the priority of the topological development is motivated by the number of output voltage levels, overall voltage gain, and full dc-link voltage utilization, while reducing the component counts and stress on devices for better efficiency and power density. To facilitate the direction of future research in SC-MLIs, this article presents a comprehensive review, critical analysis, and categorization of the existing topologies. Common fundamental units are generalized and summarized with their merits and demerits. Ultimately, major challenges and research directions are outlined leading to the future technology roadmap for more practical applications.

Predictive Control of Grid-Connected Modified-CHB With Reserve Batteries in Photovoltaic Application Under Asymmetric Operating Condition

The system stability and injection of maximum active power to the grid are among the most important technical issues in cascaded H-bridge (CHB) based photovoltaic (PV) systems, especially when the irradiation of PV arrays connected to CHB cells are not uniform. In other words, the unequal irradiation of PV arrays leads to the unbalanced output power of H-bridge cells, which causes overmodulation and increased grid current total harmonic distortion in the CHB inverter. Conventional control methods cannot maintain the stability of a grid-connected CHB inverter under asymmetric operating conditions. So, this article proposes a new CHB-based structure with reserve batteries and a novel modulation technique to stabilize the system in heavy mismatching conditions and avoid overmodulation. Furthermore, the number of switches and series batteries is reduced, and the number of output voltage levels is increased compared to the conventional PV-CHB system with energy storage. The validity of the proposed solution is verified by simulation in MATLAB/Simulink, and then the experimental results are presented to confirm the theoretical and simulation results.

Modified W-type configuration for a single-phase reduced parts count 81-level inverter.

The technology of modern power systems is revolutionizing as renewable energy sources are being integrated with electric power grids. In the form of inverters, power electronic converters are becoming an integral part of power systems due to their massive demand for grid integration of photovoltaic (PV) systems. Existing multilevel inverter topologies either require an output filter to get a sinusoidal voltage or generate a higher number of output voltage levels at the expense of many hardware resources. This paper presents a new single-phase 81-level inverter configuration with the name given as 'Modified W-Type Multilevel Inverter'. The proposed inverter configuration uses only eighteen power switches and four DC voltage sources to generate an 81-level output voltage approaching a sinusoidal waveform without an output filter. The general design equations are developed to calculate the number of switches, the number of voltage levels, and the number of DC sources for the proposed configuration. Loss and efficiency analysis is carried out that verifies a good practical efficiency of the proposed inverter configuration during the dynamic operation. A comparative analysis with the existing MLI topologies is also carried out that validates the effectiveness and novelty in reducing parts count and higher number of voltage levels. The proposed topology offers 1.04% total harmonic distortion of the output voltage which is within the benchmarks specified for grid integration without any filter requirements. The proposed inverter configuration is simulated in MATLAB/Simulink, and the results are validated by the design and development of a hardware prototype.

Motor Stator Insulation Stress Due to Multilevel Inverter Voltage Output Levels and Power Quality

Multilevel Inverters (MLIs) are widely sought after in medium-voltage applications like electric ships, electric aircraft, and renewable energy integration due to excellent advantages like lower device stress, better power quality, and modularity. However, non-sinusoidal excitations from MLIs pose a serious problem to motor-insulation and lead to their premature breakdown. This paper investigates stress in medium-voltage motor insulation when the stator winding is excited by 3-, 5-, and 7-level multilevel inverter output waveforms. The effect of firing angle on insulation stress is also studied for each of the multilevel inverters. Results show that in addition to the number of output voltage levels, PWM wave shape is a critical factor which affects the insulation stress. Both these factors work together to impact the insulation health. A strong correlation is shown between the increase in the voltage root mean square (RMS) value and increase in dielectric stress when ignoring the dv/dt impact for a fixed DC input voltage and operating frequency of the inverter. Similarly, the dielectric stress in the stator insulation increased with an increase in firing angle for each of the MLIs. This paper shows a potential that both the RMSs can be optimized to reduce the insulation stress and improve the power quality of MLIs in medium voltage drives.

Improved modified a multi-level inverter with a minimum total harmonic distortion

Renewable energy sources are developed as a result of the increased demand for electrical power. The nature of the solar energy source is DC. The DC source for many applications needs to be converted to AC. The inverter is used to convert the power from DC to AC. Total harmonic distortion (THD) is a significant concern with inverters. Multi-level inverters are used to reduce the THD. The stair output voltage of the multi-level inverter not only reduces the THD but also reduces the switches' stresses, so a low voltage rating can be used for the switches. In this paper, a modified inverter topology is introduced in which the number of switches is reduced for the same number of output voltage levels, which leads to reducing the losses and the cost. To reduce the THD, different amplitudes for the carrier signals that control the switches in each level are suggested. Another method to reduce the THD by using different capacitor values across the input DC source is presented. The MATLAB/Simulink is used to show the validity of the suggested modified topology and the modifications.

The Main objective of this project is to develop a power management system that will control the power flow and energy demand of an integrated renewable energy system with the focus on solar energy and wind energy. These storage systems are needed to provide high reliability and control systems are necessary for the stable and optimal operation of the whole

A new multilayer inverter topology is proposed in this study. The cascaded feature is used in this innovative topology. In addition to the isolated DC sources seen in Cascaded H-bridge. The clamping diode in Diode and the multilevel inverter (CHB-MLI) Inverter with Clamped Multilevel (DC-MLI). With these advantages, an inverter topology with 18 total component counts when coupled had been discovered. This proposed topology has the potential to generate up to According to the ratio allocated to its DC sources, there are 17 output levels. Aside from increasing the number of output voltage levels, this study has a relatively low number of component counts. The THD limit defined by IEEE standard is also a goal (i.e. 5 percent) all voltage applications under 69kV.To ensure that the suggested topology is functional, it is being simulated in Matlab/Simulink with various modulation indexes. The amount of THD, the number of voltage outputs, and the RMS voltage are all being monitored and discussed. Finally, to assess the uniqueness of the suggested topology, a comparison study with recently disclosed topologies is being carried out.

Model Predictive Control Scheme of a Four-Level Quasi-Nested Converter Fed AC-Drive, with dc-Link Voltage-Drift Compensation

In this paper, a Model Predictive Control (MPC) strategy is introduced for its application in a four-level quasi-nested topology, feeding an Interior Permanent Magnet Synchronous Machine (IPMSM) AC-drive. The proposed control strategy is capable to synthesize the required output space vectors to ensure perfect tracking of the AC-drive speed reference under different loading conditions, while also ensuring voltage balance between the dc-link capacitors. The proposed converter topology is based on a reduced number of components compared to other mature converter topologies, such as the neutral-point clamped converter (NPC) or the active neutral-point clamped converter (ANPC) topologies, when compared in terms of the number of output voltage levels, since this quasi-nested topology does not require passive clamping devices such as diodes or active switches. Moreover, no floating dc-link capacitors with asymmetrical voltage levels are employed, thus simplifying the dc-link capacitor voltage balance mechanism. This work presents the switching operation principles and MPC control law when supplying an IPMSM AC-drive load are addressed in detail. Simulation and validation results using a Hardware in the Loop (HIL) prototype under different operation conditions are presented in order to validate the proposed converter topology and control strategy.

Design and Analysis of Cascaded Hybrid-Bridge Multi-Cell Multilevel Inverter with Reduced Total Harmonic Distortion Profile

This multilevel inverter methodology is the center of focus among researchers in recent era. It has been focused due to its advantages over existing topologies, drawbacks and improvement of power quality, Multi-level inverter has the ability to generate nearly sinusoidal waves. This sinusoidal wave can be further improved by increasing the level of output voltage or with the help of filter design, and this manuscript presents single-phase Multi cell Multi-Level Inverter (MLI). It has been considered for reducing component count to get a higher number of output voltage levels and lower Total harmonics distortion profile. It comprises with four symmetric DC input voltage and 10 IGBT switches to produces stepped output of 9 level, and when deploy asymmetric Dc voltage source the same circuit will produce 31 level output with some changes in firing scheme, moreover this circuit is the family of cascaded hybrid bridge inverter so this circuit covered advantage of CHB MLI, This circuit uses lower no. of switch as compared to existing conventional MLIs such as FC-MLI, CHB-MLI, NPC-MLI, This paper also provides one of most pertinent controls and modulation mechanisms for a MLI using a hybrid reference/carrier-oriented sinusoidal PWM mechanism. At last, simulated outcomes are to validate the performance of both architectures in MLI structure as well as verify the concept.

Implementation of Integer Factor based Space Vector PWM through Digital approach for Grid Connected Multilevel Inverters

Space vector pulse width modulation control for grid connected multilevel inverters are very popular. However, it gets exceedingly tough with the increase in the number of output voltage levels. The total number of possible switching states will increase with the output voltage level of the inverter. Due to increase in the number of switching states, the sub triangles in the various sectors of the hexagon will also increase, that result in increased complexity and storage requirements for implementation using conventional space vector methods. The objective of the paper is to simplify and generalize the space vector algorithm for an n-level inverter. The proposed algorithm uses integer factor approach to find the exact location of the reference vector, synthesize switching times and generate the nearby switching states. It is a generalized algorithm applicable to any sequence and can be applied to any level judiciously. In this article description of the algorithm is given for a three–level inverter and validated by implementing experimentally using dspace control desk. The PWM signals generated by three level Space Vector algorithm with conventional switching sequence of 0127 is used to control an open end winding induction motor fed with two two-level inverters. The performance factor of motor voltage and line current THD at different modulation index is measured and compared with simulation result.

The New Topology of Multilevel Inverter with Less Number of Switches

A new multilayer inverter topology is proposed in this study. The cascaded feature is used in this innovative topology. In addition to the isolated DC sources seen in Cascaded H- bridge. The clamping diode in Diode and the multilevel inverter (CHB-MLI) Inverter with Clamped Multilevel (DC-MLI). With these advantages, an inverter topology with 18 total component counts when coupled had been discovered. This proposed topology has the potential to generate up to According to the ratio allocated to its DC sources, there are 17 output levels. Aside from increasing the number of output voltage levels, this study has a relatively low number of component counts. The THD limit defined by IEEE standard is also a goal (i.e. 5 percent) all voltage applications under 69kV. To ensure that the suggested topology is functional, it is being simulated in Mat lab/Simulink with various modulation indexes. The amount of THD, the number of voltage outputs, and the RMS voltage are all being monitored and discussed. Finally, to assess the uniqueness of the suggested topology, a comparison study with recently disclosed topologies is being carried out.

Aswitched‐capacitorbased multilevel inverter with reduced circuit components and voltage boosting capability

In this paper a novel topology of switched capacitor based multilevel inverters is proposed. In this topology, to increase the output voltage levels and to add the voltage boosting capability, several switched capacitor units are cascaded in series. Having voltage boosting capability and generating maximum number of output voltage levels using minimum number of circuit components, is a merit for this topology. To highlight the attributes of the proposed topology, it is compared with other recently proposed multilevel inverters on number of circuit components such as power electronic switches, diodes and capacitors, voltage boosting capability, total standing voltage, cost and efficiency. The comparison results verify the superiority of the proposed topology over other proposed topologies on number of circuit components, and number of output voltage levels. It is also clear that, this topology has lower voltage stress on power electronic switches, which makes it an appropriate solution for industrial applications. Finally, to show the capabilities of the proposed topology, and to verify the accurate operation of the topology, circuit analysis as well as the experimental results are provided.

Step-up switched-capacitor multilevel inverter employing multiple inputs with reduced switches

A large device count, weak boosting capability, and DC voltage imbalance are common issues in conventional multilevel inverters. In this paper, a novel multilevel inverter is presented that can generate the desired number of output levels with reduced devices by using new switched-capacitor circuits (SCCs). The two input sources and capacitors in the SCC can be switched in parallel and series modes. In the parallel mode, the capacitor voltage of the SCC is charged to the DC source voltage, which inherently solves the capacitor voltage imbalance issue without any auxiliary circuits. In the series mode, the capacitor can be used as an alternative source, which helps achieve a high voltage gain. The multiple input sources of the SCC make the proposed topology suitable for application in renewable energy generation systems where several DC sources are available. Instead of an H-bridge module, a structure with two half-bridges and two switches is used as a polarity generation circuit at the load terminal. The input sources of two SCCs can be selected as symmetric and asymmetric patterns, which can result in a great number of output voltage levels. The circuit topology, operational principle, modulation strategy, capacitor analysis, and performance comparisons of the inverter are described in this paper. In addition, experimental results verify the feasibility and validity of the inverter.