Number Of Nanowires Research Articles

Catalyst-free growth of ZnO nanowires on various-oriented sapphire substrates by pulsed-laser deposition

Catalyst-free growth of one-dimensional zinc oxide (ZnO) nanowires is reported. ZnO nanowires were synthesized on ZnO buffer layers deposited on various-oriented sapphire substrates. Syntheses of ZnO buffer layers and nanowires were performed by ultraviolet pulsed-laser deposition. ZnO nanowire's number density was the lowest in the case of using m-cut sapphire substrates. ZnO nanowires grown on a-cut sapphire substrates had vertical alignment with distances of tens to hundreds of nanometers. On the other hand, ZnO nanowires grown on c-cut sapphire substrates had the biggest nucleation rate. The dependence of crystalline orientation of ZnO buffer layers on the orientation of sapphire substrates were investigated by electron back scatter diffraction measurement. From their results, the growth models of ZnO buffer layers were suggested and the variations in morphological properties of ZnO nanowires were discussed.

Direct Observation of Self-Heating in III–V Gate-All-Around Nanowire MOSFETs

Gate-all-around (GAA) MOSFETs use multiple nanowires (NWs) to achieve target $I_{\mathrm{{\scriptscriptstyle ON}}}$ , along with excellent 3-D electrostatic control of the channel. Although the self-heating effect has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and specialized test structures, do not offer adequate spatiotemporal resolution. In this paper, we develop an ultrafast high-resolution thermoreflectance (TR) imaging technique to: 1) directly observe the increase in local surface temperature of the GAA-FET with different number of NWs; 2) characterize/interpret the time constants of heating and cooling through high-resolution transient measurements; 3) identify critical paths for heat dissipation; and 4) detect in situ time-dependent breakdown of individual NW. Combined with the complementary approaches that probe the internal temperature of the NWs, the TR-images offer a high-resolution map of self-heating in the surround-gate devices with unprecedented precision, necessary for the validation of electrothermal models and the optimization of devices and circuits. In addition, we develop the simple compact model of the complex structure, which can explain experimental observations and can provide the internal temperature of the NWs.

Coaxial multishell nanowires with high-quality electronic interfaces and tunable optical cavities for ultrathin photovoltaics

Silicon nanowires (NWs) could enable low-cost and efficient photovoltaics, though their performance has been limited by nonideal electrical characteristics and an inability to tune absorption properties. We overcome these limitations through controlled synthesis of a series of polymorphic core/multishell NWs with highly crystalline, hexagonally-faceted shells, and well-defined coaxial (p/n) and p/intrinsic/n (p/i/n) diode junctions. Designed 200-300 nm diameter p/i/n NW diodes exhibit ultralow leakage currents of approximately 1 fA, and open-circuit voltages and fill-factors up to 0.5 V and 73%, respectively, under one-sun illumination. Single-NW wavelength-dependent photocurrent measurements reveal size-tunable optical resonances, external quantum efficiencies greater than unity, and current densities double those for silicon films of comparable thickness. In addition, finite-difference-time-domain simulations for the measured NW structures agree quantitatively with the photocurrent measurements, and demonstrate that the optical resonances are due to Fabry-Perot and whispering-gallery cavity modes supported in the high-quality faceted nanostructures. Synthetically optimized NW devices achieve current densities of 17 mA/cm(2) and power-conversion efficiencies of 6%. Horizontal integration of multiple NWs demonstrates linear scaling of the absolute photocurrent with number of NWs, as well as retention of the high open-circuit voltages and short-circuit current densities measured for single NW devices. Notably, assembly of 2 NW elements into vertical stacks yields short-circuit current densities of 25 mA/cm(2) with a backside reflector, and simulations further show that such stacking represents an attractive approach for further enhancing performance with projected efficiencies of > 15% for 1.2 μm thick 5 NW stacks.

High‐Performance Integrated ZnO Nanowire UV Sensors on Rigid and Flexible Substrates

AbstractDue to the large surface area‐to‐volume ratio and high quality crystal structure, single nanowire (NW)‐based UV sensors exhibit very high on/off ratios between photoresponse current and dark current. Practical applications require a large‐scale and low‐cost integration, compatibility to flexible electronics, as well as reasonably high photoresponse current that can be detected without high‐precision measurement systems. In this paper, NW‐based UV sensors were fabricated in large‐scale by integrating multiple NWs connected in parallel via the contact printing method. Linear scaling of the photoresponse current with the number of NWs is demonstrated. Integrated ZnO NW UV sensors were fabricated on rigid glass and flexible polyester (PET) substrates at the macroscopic scale. The flexible and rigid sensors performed comparably, exhibiting on/off current ratios approximately three orders of magnitude higher than sensors made from polycrystalline ZnO thin films. Under UV irradiance of 4.5 mW cm−2 and 3 V bias, photoresponse currents and on/off current ratios for the rigid and flexible UV sensors reached 12.22 mA and 82 000, and 14.1 mA and 120 000, respectively. This result suggests that lateral integration of semiconductor NWs is an effective approach to large‐scale fabrication of flexible NW sensors that inherit the merits of single‐NW‐based systems with unaffected performance compared to using rigid substrate.

Scalable Monolithically Grown AlGaAs–GaAs Planar Nanowire High-Electron-Mobility Transistor

Monolithically grown planar nanowire (NW) high-electron-mobility transistors (NW-HEMTs) are demonstrated using self-aligned 〈110〉 GaAs NWs capped with Si-doped AlxGa1-xAs shell as the channel on semi-insulating (100) GaAs substrates. The planar Al0.35Ga0.65As-GaAs NW-HEMT with ~ 1-μm-long gate exhibits excellent dc characteristics, with extrinsic Gm of ~ 80 mS/mm and estimated intrinsic Gm of ~ 260 mS/mm, where the device width is defined as the entire periphery of the NWs. The ION/IOFF ratio is ~104 and the threshold is -1.5 V operating in depletion mode. The output current increases linearly with the number of NWs in the channel, while the threshold voltage does not change at all. This indicates excellent uniformity and scalability of the bottom-up-grown NW devices. Compared to field-effect transistors with doped NWs as channels, the structure reported here circumferences the inherent doping nonuniformity issues in NWs grown by the vapor-liquid-solid mechanism, and self-aligned lateral epitaxy nature of our NW structure makes scaling up to NW array-based transistors from the bottom up feasible.

Monolithic Integration of Silicon Nanowires With a Microgripper

Si nanowire (NW) stacks are fabricated by utilizing the scalloping effect of inductively coupled plasma deep reactive ion etching. When two etch windows are brought close enough, scallops from both sides will ideally meet along the dividing centerline of the windows turning the separating material column into an array of vertically stacked strings. Upon further thinning of these NW precursors by oxidation followed by oxide etching, Si NWs with diameters ranging from 50 nm to above 100 nm are obtained. The pattern of NWs is determined solely by photolithography. Various geometries ranging from T-junctions to circular coils are demonstrated in addition to straight NWs along specific crystallographic orientations. The number of NWs in a stack is determined by the number of etch cycles utilized. Due to the precise lithographic definition of NW location and orientation, the technique provides a convenient batch-compatible tool for the integration of NWs with MEMS. This aspect is demonstrated with a microgripper, where an electrostatic actuation mechanism is simultaneously fabricated with the accompanying NW end-effectors. Mechanical integrity of the NW-MEMS bond and the manipulation capability of the gripper are demonstrated. Overall, the proposed technique exhibits a batch-compatible approach to the issue of micronanointegration.

Nanowire addressing with randomized-contact decoders

Methods for assembling crossbars from nanowires (NWs) have been designed and implemented and methods for controlling individual NWs within a crossbar have also been proposed. However, implementation remains a challenge. A NW decoder is a device that controls many NWs with a much smaller number of lithographically produced mesoscale wires (MWs). Unlike traditional demultiplexers, all proposed NW decoders are assembled stochastically. In a randomized-contact decoder (RCD), for example, field-effect transistors are randomly created at about half of the NW/MW junctions. In this paper, we tightly bound the number of MWs required to produce a correctly functioning RCD with high probability. We show that the number of MWs is logarithmic in the number of NWs, even when manufacturing errors occur. We also analyze the overhead associated with controlling a stochastically assembled decoder. As we explain, lithographically-produced control circuitry must store information regarding which MWs control which NWs. This requires more area than the MWs themselves, but has received little attention elsewhere. Finally we analyze several simple testing algorithms for configuring this control circuitry. We demonstrate an unexpected tradeoff between testing time and the number of MWs required by an RCD.

Suspended nanostructures grown by electron beam-induced deposition of Pt and TEOSprecursors

Suspended nanostructures (SNSs) are grown by electron beam-induced deposition (EBID)of Pt and tetra-ethyl-ortho-silicate (TEOS) gas precursors on nanopillar tips, by lateralshifting of a scanning electron microscope beam. Shape evolution of SNSs is characterized as afunction of electron energy (5, 10, 15 keV) and electron charge deposited per unit length (CDL,1–9 pC nm−1 range) along the beam track. Pt SNSs grow as single nanowires, evolving fromthin (15–20 nm) and horizontal to thick (up to 70 nm) and inclined (up to60°) geometry as CDL increases. TEOS SNSs consist of multiple nanowires arranged in astack: horizontal and parallel along the beam shift direction and aligned on top ofeach other along the beam incidence axis. As the CDL increases, the number ofnanowires increases and the top edge of the stack progressively inclines, takingthe form of a hand-fan. Deposition yield and overall size of SNSs are found tobe proportional to CDL and inversely proportional to electron energy for bothPt and TEOS precursors. As an example of 3D nanoarchitectures achievableby this lateral EBID approach, a ‘nano-windmill’ TEOS structure is presented.