Number Of Memristors Research Articles

Advantages And Applications of Neural Hardware Based on Synapse Structure

The increasing demand of computing power serves as a motivation for researchers to develop new types of hardware structures, among which the brain-inspired chip hardware show higher potential on computing power and energy consumption over traditional types. Memristors, which serve as a representative example of them, can allows a certain amount of current to pass safely and "remembers" the previous resistance value of the device after a power failure, which can be used as a perfect similar unit of neurons. Memristor can be manufactured by multiple material, such as various kind of metal oxides and have different of structure, classified by the number of memristors in each structure. However, the synaptic structure also faces great challenge to overcome, such as the uniformity of the capacity of each synaptic unit. In conclusion, memristor-based synapses for computing neural morphology have great potential for multiple applications, which can be perfect apply to the artificial intelligence industry.

A Highly Robust Binary Neural Network Inference Accelerator Based on Binary Memristors

Since memristor was found, it has shown great application potential in neuromorphic computing. Currently, most neural networks based on memristors deploy the special analog characteristics of memristor. However, owing to the limitation of manufacturing process, non-ideal characteristics such as non-linearity, asymmetry, and inconsistent device periodicity appear frequently and definitely, therefore, it is a challenge to employ memristor in a massive way. On the contrary, a binary neural network (BNN) requires its weights to be either +1 or −1, which can be mapped by digital memristors with high technical maturity. Upon this, a highly robust BNN inference accelerator with binary sigmoid activation function is proposed. In the accelerator, the inputs of each network layer are either +1 or 0, which can facilitate feature encoding and reduce the peripheral circuit complexity of memristor hardware. The proposed two-column reference memristor structure together with current controlled voltage source (CCVS) circuit not only solves the problem of mapping positive and negative weights on memristor array, but also eliminates the sneak current effect under the minimum conductance status. Being compared to the traditional differential pair structure of BNN, the proposed two-column reference scheme can reduce both the number of memristors and the latency to refresh the memristor array by nearly 50%. The influence of non-ideal factors of memristor array such as memristor array yield, memristor conductance fluctuation, and reading noise on the accuracy of BNN is investigated in detail based on a newly memristor circuit model with non-ideal characteristics. The experimental results demonstrate that when the array yield α ≥ 5%, or the reading noise σ ≤ 0.25, a recognition accuracy greater than 97% on the MNIST data set is achieved.

A Memristive Multiplier Using Semi-Serial IMPLY-Based Adder

Memristors are among emerging technologies with many promising features, which makes them suitable not only for storage purposes but also for computations. In this work, focusing on in-memory computations, we first present our semi-serial IMPLY-based adder and perform an extensive analysis of its merits. In addition to providing a favorable balance between the number of steps and number of memristors, a key property of the presented adder is its compactness as compared to the state-ofthe-art adders. Next, using our semi-serial adder, we propose an IMPLY-based multiplier. We show that the proposed multiplier is more than 5× better than other works based on the figure of merit which gives equal weight to the number of steps (i.e., speed) and required die area. Additionally, we provide a deeper insight into IMPLY-based arithmetic units, their properties, design characteristics, and advantages or disadvantages compared to one another by proposing new figures of merit and performing comprehensive comparative analyses. This facilitates the process of design, or selection, of suitable units for the design engineers and researchers in the field.

A memristor-CMOS-based general-logic circuit and its applications

Memristors are a kind of information-storage device with resistance-switching dynamics. Due to the variable conductivity of memristive devices, their composite circuits can be used for implementation of logic operations. In this paper, a novel hybrid CMOS-memristor-based logic circuit is proposed for use in realizing four basic logic operations (AND, OR, XOR, XNOR) simultaneously within the same circuit. Compared with existing logic implementations (MAD Gates, MRL, IMPLY), the present circuit offers better performance and greater efficiency, owing to the significant reduction in the number of memristors used in the circuit and the power consumption. Thus, a new full-adder circuit and a binary-image-encryption circuit are designed. Unlike previous full-adder circuits, the proposed one has great advantages in terms of the number of circuit elements. In the proposed encryption circuit, there are two available encryption methods and the encryption key is independent of the circuit, which can improve the reliability of encryption results.

Single Crossbar Array of Memristors With Bipolar Inputs for Neuromorphic Image Recognition

In this paper, we propose a new crossbar architecture of memristors with bipolar inputs for an image recognition application. The performance of the proposed crossbar array with bipolar inputs is based on the simplified Exclusive-NOR function to measure the similarity between the input pattern and the stored patterns. In the proposed architecture, only one crossbar array is used instead of two crossbar arrays. The number of memristors in the proposed architecture is reduced by 50%, when compared to the complementary and the twin architectures. The proposed crossbar architecture with bipolar inputs consumes 16.7% and 7.2% less power than do the complementary and twin architectures. In addition, using only one crossbar array in the proposed architecture can improve the fault tolerance of the crossbar circuit. When 10% of memristors are defective, the proposed crossbar architecture shows a recognition rate improved by 5%, 7% and 4% over that of the memristor binarized neural network, the complementary architecture of the memristor crossbar and the twin architecture of the memristor crossbar when recognizing 10 images.

Multilayer Neural Network with Synapse Based on Two Successive Memristors

Introduction: Synapse based on two successive memristors builds the synaptic weights of the artificial neural network for training three-bit parity problem and five-character recognition. Methods: The proposed memristor synapse circuit creates positive weights in the range [0;1], and maps it to range [-1;1] to program both the positive and negative weights. The proposed scheme achieves the same accuracy rate as the conventional bridge synapse schemes which consist of four memristors. Results and Conclusion: However, proposed synapse circuit decreases 50% the number of memristors and 76.88% power consumption compared to the conventional bridge memristor synapse.

New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing

In this paper, we propose a new memristorbased crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.

Dimensionality reduction modeling and characteristic analysis of memristive circuit

Through mathematical modeling analysis of Chua’s memristive circuit, the problem of dimensionality reduction for dynamical modeling of memristive circuit is proposed. Taking memristive circuit with two memristors for example, dimensionality reduction modeling of the memristive circuit is performed, on which a three-dimensional system model is established. Based on this model, the equilibrium points and stabilities are analyzed, and the dynamical characteristics, when the parameters are varied, are investigated. Furthermore, the analysis results from the conventional model are compared with the results from the dimensionality reduction model of memristive cicuit with two memristors. The results indicate that the dimensionality of the dimensionality reduction model of memristive circuit is related to the number of capacitors and inductors only, but unrelated to the number of memristors; there exist nonlinear phenomena about the coexistence of bifurcation modes in the memristive circuit when circuit parameters are varied; the dimensionality reduction modeling reduces the complexity of system modeling, which is conducive to dynamical charateristic analysis of the system but eliminates the effect of the initial conditions of the memristors internal state variables on dynamical charateristics of memristive circuit.

Memristive port-Hamiltonian Systems

The port-Hamiltonian modelling framework is extended to a class of systems containing memristive elements and phenomena. First, the concept of memristance is generalised to the same generic level as the port-Hamiltonian framework. Second, the underlying Dirac structure is augmented with a memristive port. The inclusion of memristive elements in the port-Hamiltonian framework turns out to be almost as straightforward as the inclusion of resistive elements. Although a memristor is a resistive element, it is also a dynamic element since the associated Ohmian laws are rather expressed in terms of differential equations. This means that the state space manifold, as naturally defined by the storage elements, is augmented by the states associated with the memristive elements. Hence the order of complexity is, in general, defined by the number of storage elements plus the number of memristors in the system. Apart from enlarging our repertoire of modelling building blocks, the inclusion of memristive elements in the existing port-Hamiltonian formalism possibly opens up new ideas for controller synthesis and design.