Number Of Memory Controllers Research Articles

Walter: Wide I/O Scaling of Number of Memory Controllers Versus Frequency and Voltage

Computational application demands do push the scaling of the number of cores, which themselves further increase the demand for more bandwidth. The use of larger rank widths and/or scaling the number of memory controllers (MCs) is a straightforward way to increase memory bandwidth. Connecting wide ranks and MCs via low-capacitance Through Silicon Vias (TSVs) favors high-bandwidth 3DStacking systems (e.g. Wide I/O). Given that voltage and frequency scaling (VFS) lower power utilization but the use of lower clock frequencies reduces bandwidth, this article proposes Walter as a Wide I/O technique that trades off scaling of the number of memory controllers (MCs) versus clock frequency and voltage (VFS) to mitigate low bandwidth and improve energy-per-bit usage. Our findings show that Walter's Wide I/O architectural benefits of using a larger number of MCs coupled with wider ranks when combined to VFS are promising: compared to the baseline for a 75% frequency/voltage reduction, MC scalability improved memory bandwidth by 2.4x and energy-per-bit reduced by 20% (most benchmarks for up to 16 MCs). Walter's architectural replacement of ranks set at specification frequencies with ones set at lower frequencies allows temperature reduction thus likely allowing further rank stacking.

An analytical model for thread-core mapping for tiled CMPs

Modern computing chips are composed of multiple, simple, low-power processing cores. Increasing the number of processing cores in a single chip brings the opportunity to exploit the inherent massive level of thread parallelism and further improved performance. However, efficient allocation of applications (threads) to available cores is a complicated process. Failing to do so, the mapping can be the limiting factor for achieving better performance on a tiled chip-multiprocessor (CMP). In this paper, we propose a mathematical formulation based on mixed integer linear program (MILP) to map application threads on cores at worst-case scenario by keeping into account the spatial topology of a two-dimensional mesh (2D-mesh) Networks-on-Chip (NoC). Our model allows evaluating in absolute term the performance of different mapping and routing algorithms. The proposed analytical model is general enough to consider a different optimising policy from energy to latency and a different number of memory controllers. In the experiments, we have shown that the proposed approach can achieve up to 40% reduction over the traditional zig-zag heuristic, therefore showing that there is a range for improving application mapping.

RAMON: Region-Aware Memory Controller

Recent implementations of heterogeneous multicore systems [central processing unit (CPU), graphics processing unit (GPU), and hybrid] address the issue of communication latency between CPU and GPU memory systems by merging these two, so that they can share the same memory address space. In recent years, the combination of the escalation in the number of cores with the rise in memory-intensive applications has significantly increased bandwidth (Bw) needs in both homogeneous and heterogeneous systems. Since tasks assigned to CPU and/or GPU cores will have different Bw demands, a two-tier memory system is needed. Hence, in this paper, Region-Aware Memory cONtroller (RAMON) is proposed as a configurable memory system where different address space regions are able to be dedicated to a different number of memory controllers (MCs), concurrently to supply different amounts of Bw to a different number of cores, providing different levels of memory parallelism. By having different address space regions—simply regions, each with a different number of MCs to match its Bw needs, memory interference per region is reduced. Our findings show that RAMON is promising and improves Bw by a factor of 9 times for CPU regions, 14.1 times for GPU regions, and 4.5 times for combined heterogeneous regions.

Exploiting dynamic transaction queue size in scalable memory systems

In order to increase parallelism via memory width in scalable memory systems, a straightforward approach is to employ larger number of memory controllers (MCs). Nevertheless, a number of researches have pointed out that, even executing bandwidth-bound applications in systems with larger number of MCs, the number of transaction queue entries is under-utilized—namely as shallower transaction queues, which provides an opportunity to power saving. In order to address this challenge, we propose the use of transaction queues with dynamic size that employs the most adequate size, taking into consideration the number of entries utilized while presenting adequate levels of bandwidth and minimizing power. Experimental results show that, while saving up to 75% number of entries, the introduction of dynamic transaction queue mechanism can present savings up to 75% of bandwidth and 20% of rank energy-per-bit reduction compared to systems with 1–2 entries.

System implications of LLC MSHRs in scalable memory systems

By exploring the scalability of memory controllers (MCs) and ranks in scalable memory systems, larger degrees of memory bandwidth are offered when scaling cores in traditional multicores and embedded systems, and the ratio computation versus memory width - expressed as ratio between the number of cores and MCs - favors the former in detriment to the latter. In scalable memory systems, this ratio tends to balance the number of cores and MCs. Furthermore, since each core has their Last Level Cache (LLC) strongly subject to the number of Miss Status Holding Registers (MSHRs) present, which retain information on all outstanding misses of a specific cache line, it is fundamental to evaluate the impact of these elements in scalable memory systems. Experimental results show that, as reducing the number of MSHRs, memory bandwidth levels are reduced by about 64% and rank energy-per-bit levels are increased of about 36% for different patterns.