Number Of Loop Iterations Research Articles

Potential and methods for embedding dynamic offloading decisions into application code

A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop iterations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading decisions into the application code. We perform in-depth static and dynamic analysis of popular benchmarks, which confirm the general potential of such an approach. We also propose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes.

Analysis of Linear Definite Iterative Loops

The paper presents a new method to prove the invariance of the system of linear inequalities and completability of linear definite iterative loops for imperative programs. Loop body is a linear operator that transforms the vector of program variables. The method takes into account loop precondition, as well as the condition of loop repetition in the form of a set of systems of linear inequalities. The method is based on the construction and analysis of the spectrum of linear operator and calculation of the number of loop iterations after which the invariance is either provided or disproved. The theory is illustrated by examples.

DAG inlining: a decision procedure for reachability-modulo-theories in hierarchical programs

A hierarchical program is one with multiple procedures but no loops or recursion. This paper studies the problem of deciding reachability queries in hierarchical programs where individual statements can be encoded in a decidable logic (say in SMT). This problem is fundamental to verification and most directly applicable to doing bounded reachability in programs, i.e., reachability under a bound on the number of loop iterations and recursive calls. The usual method of deciding reachability in hierarchical programs is to first inline all procedures and then do reachability on the resulting single-procedure program. Such inlining unfolds the call graph of the program to a tree and may lead to an exponential increase in the size of the program. We design and evaluate a method called DAG inlining that unfolds the call graph to a directed acyclic graph (DAG) instead of a tree by sharing the bodies of procedures at certain points during inlining. DAG inlining can produce much more compact representations than tree inlining. Empirically, we show that it leads to significant improvements in the running time of a state-of-the-art verifier.

Modeling flow information of loops using compositional condition of controls

This paper proposes a flow analysis approach to provide accurate flow facts such as number of loop iterations and infeasible paths for WCET analysis. To achieve this, a novel approach to model program flows of given loops as compositional condition of controls that can model the program flow of the sequence of basic blocks on an execution path through a single loop iteration is proposed. The proposed approach builds distinct symbolic expressions each representing a path condition as conjunctions of branch conditions along the path. Then, the path conditions are formed via substituting all constituent variables of the branch conditions with symbolic expressions computing the value of these variables. The final symbolic expression will contain variables denoting theirs value at the loop entry point. Considering the change in the value of the loop variables of the path condition, the feasible values of these variables are computed and consequently the number of the loop iterations along the iteration path is determined. Applying a SMT solver to the symbolic expressions representing each path condition, all the infeasible paths along the loop body are detected. The results of applying our flow analysis approach to a number of programs addressed in the Malardalen benchmark suite reveal the capability and efficiency of our proposed approach.

Infinite Loop Detection Based on Chains of Recurrence Algebra and Convergence of Iterative Sequence

In this paper,two mathematical methods are proposed to detect the non-termination of two types of loop.The first method is based on chains of recurrence algebra.It is for detecting the non-termination of the loops in which the basic iterative relations of variables are linear or geometrical.All the variables in the loop are unified representation by the Chains of Recurrence Algebra(CR).Then the closed-form function of the loop condition about the number of loop iteration is deduced by the rules of CR.According to it the non-termination of loops can be decided through the monotonicity of the closed-form function and constraint solver.The second method is based on convergence of iterative sequence,which is for detecting the non-termination of the nonlinear loop.According to the convergence of iterative function and fixed-point we can determine the non-termination of the loops.In experiments,we analyzed 52loops which were presented by Velroyen[20]and 23loops which are from articles[18-19,21-23]and 13loops which are created by ourselves.The experimental results show that it can detect the non-termination of loop effectively.It can give the variable constraints which make the loop non-terminated.Meanwhile the number of loop iterations can be estimated when the loop is terminated.

Recognizing Plans with Loops Represented in a Lexicalized Grammar

This paper extends existing plan recognition research to handle plans containing loops. We supply an encoding of plans with loops for recognition, based on techniques used to parse lexicalized grammars, and demonstrate its effectiveness empirically. To do this, the paper first shows how encoding plan libraries as context free grammars permits the application of standard rewriting techniques to remove left recursion and ε-productions, thereby enabling polynomial time parsing. However, these techniques alone fail to provide efficient algorithms for plan recognition. We show how the loop-handling methods from formal grammars can be extended to the more general plan recognition problem and provide a method for encoding loops in an existing plan recognition system that scales linearly in the number of loop iterations.

An Improvement of Twisted Ate Pairing Efficient for Multi-Pairing and Thread Computing

In the case of Barreto-Naehrig pairing-friendly curves of embedding degree 12 of order r, recent efficient Ate pairings such as R-ate, optimal, and Xate pairings achieve Miller loop lengths of (1/4)⌊log2r⌋. On the other hand, the twisted Ate pairing requires (3/4)⌊log2r⌋ loop iterations, and thus is usually slower than the recent efficient Ate pairings. This paper proposes an improved twisted Ate pairing using Frobenius maps and a small scalar multiplication. The proposed idea splits the Miller's algorithm calculation into several independent parts, for which multi-pairing techniques apply efficiently. The maximum number of loop iterations in Miller's algorithm for the proposed twisted Ate pairing is equal to the (1/4)⌊log2r⌋ attained by the most efficient Ate pairings.

Verification and falsification of programs with loops using predicate abstraction

Abstract Predicate abstraction is a major abstraction technique for the verification of software. Data is abstracted by means of Boolean variables, which keep track of predicates over the data. In many cases, predicate abstraction suffers from the need for at least one predicate for each iteration of a loop construct in the program. We propose to extract looping counterexamples from the abstract model, and to parametrise the simulation instance in the number of loop iterations. We present a novel technique that speeds up the detection of long counterexamples as well as the verification of programs with loops.

Generalizing parametric timing analysis

In the design of real-time and embedded systems, it is important to establish a bound on the worst-case execution time (WCET) of programs to assure via schedulability analysis that deadlines are not missed. Static WCET analysis is performed by a timing analysis tool. This paper describes novel improvements to such a tool, allowing parametric timing analysis to be performed. Parametric timing analyzers receive an upper bound on the number of loop iterations in terms of an expression which is used to create a parametric formula. This parametric formula is later evaluated to determine the WCET based on input values only known at runtime. Effecting a transformation from a numeric to a parametric timing analyzer requires two innovations: 1) a summation solver capable of summation non-constant expressions and 2) a polynomial data structure which can replace integers as the basis for all calculations. Both additions permit other methods of analysis (e.g. caching, pipeline, constraint) to occur simultaneously. Combining these techniques allows our tool to statically bound the WCET for a larger class of benchmarks.

Supporting Timing Analysis by Automatic Bounding of LoopIterations

Static timing analyzers, which are used to analyze real-time systems, need to know the minimum and maximum number of iterations associated with each loop in a real-time program so accurate timing predictions can be obtained. This paper describes three complementary methods to support timing analysis by bounding the number of loop iterations. First, an algorithm is presented that determines the minimum and maximum number of iterations of loops with multiple exits. Even when the number of iterations cannot be exactly determined, it is desirable to know the lower and upper iteration bounds. Second, when the number of iterations is dependent on unknown values of variables, the user is asked to provide bounds for these variables. These bounds are used to determine the minimum and maximum number of iterations. Specifying the values of variables is less error prone than specifying the number of loop iterations directly. Finally, a method is given to tightly predict the execution time of inner loops whose number of iterations is dependent on counter variables of outer level loops. This is accomplished by formulating the total number of iterations of a loop in terms of summations and solving the resulting equation. These three methods have been successfully integrated in an existing timing analyzer that predicts the performance for optimized code on a machine that exploits caching and pipelining. The result is tighter timing analysis predictions and less work for the user.

An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution

Previously published methods for estimation of the worst-case execution time on high-performance processors with complex pipelines and multi-level memory hierarchies result in overestimations owing to insufficient path and/or timing analysis. This does not only give rise to poor utilization of processing resources but also reduces the schedulability in real-time systems. This paper presents a method that integrates path and timing analysis to accurately predict the worst-case execution time for real-time programs on high-performance processors. The unique feature of the method is that it extends cycle-level architectural simulation techniques to enable symbolic execution with unknown input data values; it uses alternative instruction semantics to handle unknown operands. We show that the method can exclude many infeasible (or non-executable) program paths and can calculate path information, such as bounds on number of loop iterations, without the need for manual annotations of programs. Moreover, the method is shown to accurately analyze timing properties of complex features in high-performance processors using multiple-issue pipelines and instruction and data caches. The combined path and timing analysis capability is shown to derive exact estimates of the worst-case execution time for six out of seven programs in our benchmark suite.

On estimating the useful work distribution of parallel programs under P3T: a static performance estimator

In order to improve a parallel program's performance it is critical to evaluate how even the work contained in a program is distributed over all processors dedicated to the computation. Traditional work distribution analysis is commonly performed at the machine level. The disadvantage of this method is that it cannot identify whether the processors are performing useful or redundant (replicated) work. The paper describes a novel method of statically estimating the useful work distribution of distributed-memory parallel programs at the program level, which carefully distinguishes between useful and redundant work. The amount of work contained in a parallel program, which correlates with the number of loop iterations to be executed by each processor, is estimated by accurately modeling loop iteration spaces, array access patterns and data distributions. A cost function defines the useful work distribution of loops, procedures and the entire program. Lower and upper bounds of the described parameter are presented. The computational complexity of the cost function is independent of the program's problem size, statement execution and loop iteration counts. As a consequence, estimating the work distribution based on the described method is considerably faster than simulating or actually compiling and executing the program. Automatically estimating the useful work distribution is fully implemented as part of P3T, which is a static parameter based performance prediction tool under the Vienna Fortran Compilation System (VFCS). The Lawrence Livermore Loops are used as a test case to verify the approach.

Static Scheduling of Conditional Branches in Parallel Programs

The problem of scheduling non-deterministic graphs arises in several situations in scheduling parallel programs, particularly in the cases of loops and conditional branching. When scheduling loops in a parallel program, non-determinism arises because the number of loop iterations may not be known before the execution of the program. However, since loops from a restricted class of conditional branching, there is a higher degree of non-determinism associated with scheduling conditional branching. In this case, the direction of every branch remains unknown before run time. It follows that entire subprograms of the parallel program may or may not get executed, which in turn increases the amount of non-determinism and complicates the scheduling process. Thus, the term non-determinism is frequently associated with conditional branching in the literature. In this paper, we study the problem of constructing a static schedule for task graphs that contain conditional branching on parallel computers. Generally, it is difficult to obtain optimal solutions for solving various scheduling problems, even in the deterministic case. When non-determinism is added to the scheduling problem through conditional branching, an optimal solution will be even harder to obtain. We start the paper with a brief discussion of the scheduling problem, then we introduce a model for representing parallel programs that contain branches. We present a two-step scheduling technique which employs two different approaches: a graph theoretic appraoch and a multi-phase approach. The first approach is based on exploring several graph theoretic properties of the model. This approach is used as a preprocessing step to decrease the amount of non-determinism before applying the multi-phase approach. In the second step, several execution instances of the program are generated, a schedule for every instance is obtained, and a unified schedule is constructed by merging the obtained schedules. Finally, we report the results of the experiments that we conducted to measure the performance of the techniques introduced in this paper.

Double- and triple-step incremental linear interpolation

Incremental linear interpolation determines the set of n+1 equidistant points on an interval [a,b] where all variables involved (n, a, b, and the set of equidistant points) are integers and n>0. Our method of linear interpolation generalizes the findings of a variable-step line-drawing algorithm. The resulting interpolation algorithm has as many loops as the line-drawing algorithm, but fewer restrictions on its input variables. Furthermore, its benefits over the fixed-step interpolation algorithms are similar to those of the variable-step line-drawing algorithm. That is, the double- and triple-step interpolation algorithm can reduce the number of loop iterations of the double-step interpolation algorithm (by 12.5% on average) while keeping the code complexity, initialization costs, and worst-case performance the same. The improvement in speed over the single-step B5 algorithm is even greater. >