Number Of Level Shifters Research Articles

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS dual-rail SRAM achieves energy-savings by using a low supply voltage to precharge bitlines while minimizing the performance overhead by appropriately assigning a high-supply voltage to critical circuit blocks with effective level-shifting circuits. The sense amplifier embeds a level-shifting operation, thereby operating with a high supply voltage for a fast sensing operation. The proposed dynamic output buffer resolves the potential static current problem and improves the read delay. The number of level shifters is reduced using a proposed write driver, which conducts level-shifting and write-driving simultaneously. The proposed ELS dual-rail SRAM achieves low-power operation with 71.4% power consumption compared to single-rail SRAM with 72% performance overhead in circuit-level simulation, while the previous hybrid dual-rail SRAM shows 67.8% energy consumption with 270% performance overhead. In architecture-level simulation using Gem5 simulator with SPEC2006 benchmarks, the system with the ELS dual-rail SRAM caches shows, on average, 29% performance improvement compared to that of the system with the hybrid dual-rail SRAM caches.

A Modified Algorithm for Voltage Assignment and Floorplanning of SOC Designs

Background/Objectives: Dynamic Power reduction has become a very important issue in the design of System on Chip (SOC). One of the methods for reduction is use of multiple supply voltage (MSV). In this MSV design, the modules are placed in the contiguous region such that modules of same operating voltage are placed in a same region. Such regions are called as Voltage Island. In this process, voltage assignment is followed by floor planning to avoid geometric constraints and physical information of the design. But increase in number of voltage island causes increase in number of level shifters between voltage islands. In this paper, we consider the Intellectual Property (IP) core based Voltage Island driven floorplanning problem including voltage island reduction. Voltage island reduction is carried over by matching algorithm. Methods/Statistical Analysis: The proposed matching algorithm constructs a graph G consisting of vertices as Voltages Island and edges as connectivity between Voltage Islands. The proposed matching algorithm takes care of number of modules and interconnects in between Voltage Island while contracting the vertices. Findings: The result of proposed matching algorithm is taken as candidate solution represented by Sequence Pair technique, for floorplanning. A new genetic algorithm based optimization is proposed to give the best solution of floorplan which reduces the dynamic power. The proposed algorithms are compared with two approaches such as partitioning the modules on the critical path and partitioning the modules of same operating voltage. Experimental results show that our proposed algorithm for voltage Island reduction and floorplanning minimizes the number of level shifters and overall Dynamic Power of circuit. Applications/Improvements: The proposed algorithm plays a significant role in the developing CAD software for the SOC Design. Our future work is on developing a suitable data structure for the floorplanning for multiple voltage design which includes IR drop in power rails as constraint. We also planned to focus this issue of multiple voltage design towards 3D ICs.

Voltage Island Partitioning Based Floorplanning Algorithm

As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.

Optimal Supply Voltage Assignment under Timing, Power and Area Constraints

Multiple supply voltage (MSV) assignment is a highly effective means of reducing power consumption. Many existing algorithms perform very well for power reduction. However, they do not handle the area issue of level shifters. In some cases, although one gets a superior result to reduce the power consumption, but many extra level shifters are needed to add so that the circuit area will be over the specification. In this paper, we present an effective integer linear programming (ILP)-based MSV assignment approach to solve two problems with different objectives. For the objective of power reduction under timing constraint, compared with GECVS algorithm [10], the power consumption obtained by our proposed approach can be further reduced 0 to 5.46% and the number of level shifters is improved 16.31% in average. For the objective of power reduction under constraints of both timing and area of level shifters, the average improvement of power consumption obtained by our algorithm is still better than GECVS while reducing the number of level shifters by 22.92% in average. In addition, given a constraint of total power consumption, our algorithm will generate a design having minimum circuit delay. Experimental results show that the proposed ILP-based MSV assignment algorithm solves different problems flexibly.