Number Of Internal Scan Chains Research Articles

Predictive Techniques for Projecting Test Data Volume Compression

Test data compression is widely employed in scan design to tackle high test data volume (TDV) and test time problems. Given the number of scan-in pins available in automated test equipment, architectural decisions regarding the number of internal scan chains directly impact the compression level attained. While targeting an aggressive compression level by increasing the number of internal scan chains would reduce the TDV per encodable pattern, the cost of serially applying more patterns to restore the coverage loss offsets the compression benefits. Following up from our earlier work, we propose here a wide spectrum of predictive techniques for projecting the test cost of a given scan configuration for combinational xor-based decompression. The appropriate technique is selected by designers based on which stage the design is in, the design abstraction and the amount of information available, the permissible computational complexity of the techniques, and the accuracy of the projected optimal compression ratio.

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

IC testing based on a full-scan design methodology and ATPG is the most widely used test strategy today. However, rapidly growing test costs are severely challenging the applicability of scan-based testing. Both test data size and number of test cycles increase drastically as circuit size grows and feature size shrinks. For a full-scan circuit, test data volume and test cycle count are both proportional to the number of test patterns N and the longest scan chain length L. To reduce test data volume and test cycle count, we can reduce N, L, or both. Earlier proposals focused on reducing the number of test patterns N through pattern compaction. All these proposals assume a 1-to-1 scan configuration, in which the number of internal scan chains equals the number of external scan I/O ports or test channels (two ports per channel) from ATE. Some have shown that ATPG for a circuit with multiple clocks using the multicapture clocking scheme, as opposed to one-hot clocking, generates a reduced number of test patterns.

Concurrent application of compaction and compression for test time and data volume reduction in scan designs

A test pattern compression scheme for test data volume and application time reduction is proposed. While compression reduces test data volume, the increased number of internal scan chains due to an on-chip, fixed-rate decompressor reduces test application time proportionately. Through on-chip decompression, both the number of virtual scan chains visible to the ATE and the functionality of the ATE are retained intact. Complete fault coverage is guaranteed by constructing the decompression hardware deterministically through analysis of the test pattern set.

Test data compression using dictionaries with selective entries and fixed-length indices

We present a dictionary-based test data compression approach for reducing test data volume in SOCs. The proposed method is based on the use of a small number of ATE channels to deliver compressed test patterns from the tester to the chip and to drive a large number of internal scan chains in the circuit under test. Therefore, it is especially suitable for a reduced pin-count and low-cost DFT test environment, where a narrow interface between the tester and the SOC is desirable. The dictionary-based approach not only reduces test data volume but it also eliminates the need for additional synchronization and handshaking between the SOC and the ATE. The dictionary entries are determined during the compression procedure by solving a variant of the well-known clique partitioning problem from graph theory. Experimental results for the ISCAS-89 benchmarks and representative test data from IBM show that the proposed method outperforms a number of recently-proposed test data compression techniques. Compared to the previously proposed test data compression approach based on selective Huffman coding with variable-length indices, the proposed approach generally provides higher compression for the same amount of hardware overhead.