Number Of Extra Bits Research Articles

The Rabin cryptosystem revisited

The Rabin scheme used in public-key cryptosystem is here revisited with a focus limited to a few specific open issues. In particular, message decryption requires one out of four roots of a quadratic equation in a residue ring to be chosen, and a longstanding problem is to identify unambiguously and deterministically the encrypted message at the decryption side by adding the minimum number of extra bits to the cipher-text. While the question has already been solved for pairs of primes of the type $$4k+3$$4k+3, the general problem is here addressed. As one of the major results, an explicit solution with two extra bits is provided for pairs of primes that are congruent 5 modulo 8. The Rabin signature is also reconsidered from a deterministic point of view: a padding mechanism is proposed that avoids relying on a certain number of attempts until a suitable pad is found.

Reversible data hiding with high payload based on referred frequency for VQ compressed codes index

In 2007, Chang et al. proposed a reversible data hiding scheme for secret communication that hides secret information in the compression codes of a cover image, but their scheme has low hiding capacity and introduces extra m bits to reverse the original vector quantization (VQ) index of the cover image after the secret data are extracted. Instead of introducing m bits (where the size of the codebook is m bits) and using only one-third of the VQ indices of the cover image to hide the secret bit, we propose using only one bit to distinguish between indices of two clusters (i.e., cluster2 and cluster3). Not only the indices in cluster1 but also those in cluster2 and cluster3 can hide the secret bits. Our proposed scheme reduces the number of extra bits and increases the hiding capacity. The experiment results clearly showed that our proposed scheme outperforms Chang et al.׳s hiding scheme.

Seamless switching of scalable video bitstreams for efficient streaming

Efficient adaptation to channel bandwidth is broadly required for effective streaming video over the Internet. To address this requirement, a novel seamless switching scheme among scalable video bitstreams is proposed in this paper. It can significantly improve the performance of video streaming over a broad range of bit rates by fully taking advantage of both the high coding efficiency of nonscalable bitstreams and the flexibility of scalable bitstreams, where small channel bandwidth fluctuations are accommodated by the scalability of a single scalable bitstream, whereas large channel bandwidth fluctuations are tolerated by flexible switching between different scalable bitstreams. Two main techniques for switching between video bitstreams are proposed. Firstly, a novel coding scheme is proposed to enable drift-free switching at any frame from the current scalable bitstream to one operated at lower rates without sending any overhead bits. Secondly, a switching-frame coding scheme is proposed to greatly reduce the number of extra bits needed for switching from the current scalable bitstream to one operated at higher rates. Compared with existing approaches, such as switching between nonscalable bitstreams and streaming with a single scalable bitstream, our experimental results clearly show that the proposed scheme brings higher efficiency and more flexibility in video streaming.

Bidirectionally decodable streams of prefix code-words

A new general scheme is introduced that allows bidirectional decoding of variable length coded bitstreams from either end. Except for a small fixed number of extra bits appended to a sequence of code words, the scheme is as efficient as Huffman coding. The extra operations required at the coder and decoder are code word reversal and one EXOR for each bit.

Heaps with bits

In this paper, we show how to improve the complexity of heap operations and heapsort using extra bits. We first study the parallel complexity of implementing priority queue operations on a heap. The trade-off between the number of extra bits used, the number of processors available, and the parallel time complexity is derived. While inserting a new element into a heap in parallel can be done as fast as parallel searching in a sorted list, we show how to delete the smallest element from a heap in constant time with a sublinear number of processors, and in sublogarithmic time with a sublogarithmic number of processors. The models of parallel computation used are the CREW PRAM and the CRCW PRAM. Our results improve those of previously known algorithms. Moreover, we study a variant, the fine-heap, of the traditional heap structure. A fast algorithm for constructing this new data structure is designed using an interesting technique, which is also used to develop an improved heapsort algorithm. Our variation of heapsort is faster than Wegener's heapsort and requires less extra space.

Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers

We propose a new scheme for built-in test (BIT) that uses multiple-polynomial linear feedback shift registers (MP-LFSR's). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear equations involving the seed variables for the positions where the test cubes have specified values. We demonstrate that MP-LFSR's produce sequences with significantly reduced probability of linear dependence compared to single polynomial LFSR's. We present a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the number of polynomials. Theoretical analysis and experiments show that the probability of encoding a test cube with s specified bits in an s-stage LFSR with 16 polynomials is 1-10/sup -6/. We then present the new BIT scheme that allows for an efficient encoding of the entire test set. Here the seeds are grouped according to the polynomial they use and an implicit polynomial identification reduces the number of extra bits per seed to one bit. The paper also shows methods of processing the entire test set consisting of test cubes with varied number of specified bits. Experimental results show the tradeoffs between test data storage and test application time while maintaining complete fault coverage.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A noise resistant synchronization scheme for HDTV images

A method that increases the error resistance of the HDTV system and offers graceful picture degradation in the presence of bit errors, is presented. Due to the nature of the presently proposed compression schemes for HDTV systems, an error in a data bit does not only affect the block the bit belongs to, but unfortunately the effects of this error may perpetuate to the following blocks. This is because a bit error may cause loss of synchronization between the data bits and the picture blocks they represent. Our method restricts the effects of a bit error to a picture block whose size is significantly smaller than those used by the HDTV systems. We achieve synchronization by transmitting a header-word for each such synchronization block. Each header-word contains the number of data bits representing the compressed block. This header-word is protected by two levels of FEC code. To decrease the number of extra bits needed by the header-words, two different synchronization block sizes are used, a relatively small block size for the reference frames and a larger size for the inter-frames. The resulting method improves the quality of the picture in the presence of errors and defers the SNR at which the HDTV picture suddenly deteriorates by 2.5 to 3 dB. It also allows operation at higher order modulation transmission schemes, e.g., 32-QAM instead of 16-QAM, without the requirement of increased signal power.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A verification of brickell's fast modular multiplication algorithm

This paper refers to the algorithm and its hardware implementation described by Brickell [1] for modular multiplication in N+10 clock pulses where N is the number of bits in the binary integers involved. Brickell [1] uses a delayed carry representation which consists of two registers of N bits each—one for the uncarried carries. Of course, up to N clocks ticks may eventually be required to assimilate the carries at the end of the computation. Several sources of possible error are reported here—one in the hardware, one in the specification which the intended hardware satisfies, and one in the definition of the control variables T 1 and T 2. Our main contributions are the supply of further detail to remove such ambiguities, a determination of the minimum number of extra bits required during the calculation, a verification of the more detailed system, and its extension to an integer division procedure. The existence of a proof enables it to be used reliably for its intended purpose in applications such as cr...

A Sliding-Scale Direct-Feedback PCM Coder for Television

A sliding-scale coder for television signals was built which extends the range of the quantizing scale by processing the input signal twice when the input signal exceeds a prescribed threshold. On the second pass the quantizing range is effectively moved outward to reduce the errors in coding large signals. Double processing nearly triples the number of quantizing levels of a basic three-bit coder. Measurements of the number of extra bits required, that is, those in excess of three-bits per sample show that they may be accomodated on a three-bit per sample transmission channel by reducing the sampling rate five percent. The experimental coder generates 19 quantizing levels. Its performance approaches that of a seven-bit pulse code modulation coder. Busyness or streaking, common to most three-bit differential type coders, is eliminated. Acceptable pictures are reproduced with ±5 dB changes in the input signal's range. Over this range the signal-to-noise ratio of the reproduced pictures varies from 47 dB to 54 dB and the rise-time of a regenerated step-signal varies from 1 microsecond to 1.45 microsecond when the input signals rise-time is limited to 1 microsecond.