Number Of Data Bits Research Articles

Energy-efficient image compression algorithm for wireless sensor networks in structural health monitoring applications

In Wireless Sensor Networks (WSN), transmitting an uncompressed image consumes more energy than a compressed image, and it is, therefore, the prime requirement to establish energy-aware compression methods to extend the life of the sensor node, and ultimately the network as a whole. This work suggests an image compression algorithm with a low degree of complexity for WSNs in structural health monitoring applications. This algorithm represents a pruning approach to a Discrete Cosine Transform approximation transform in which the transformation matrix is modified to reduce the series of steps and the compression ratio achieved is better compared to the actual image which makes it easy for the data storage. Because of the reduction in the number of data bits, it enhances the lifetime of the network by reducing the number of node failures caused by resource scarcity. The implementation is tested by capturing real-time images of concrete walls in buildings using Raspberry Pi3B + WSN gateway fitted with camera modules. The scheme is also investigated in terms of a variety of parameters like Peak Signal to Noise Ratio, Mean Square Error, Structural SIMilarity Index and Compression Ratio. This technique achieves the best arbitration of energy consumption and image quality.

A Study of High-Speed Hamming Distance Detection Circuit Utilizing a Neuron CMOS Inverter

This study tackles the challenge of optimizing associative memory for efficient data retrieval from large databases, crucial in real-time processing. The authors specifically address the issue of increased detection time in the minimum Hamming distance search associative memory, particularly as the number of data bits grows. This memory system utilizes Hamming distance as a key metric to identify the most similar reference data. Our contribution is the development of a new Hamming distance detection circuit employing neuron Complementary Metal Oxide Semiconductor (CMOS) inverters. This proposed circuit significantly outperforms existing models in terms of operational speed. The effectiveness and improved performance of the circuit are validated through simulations using HSPICE, a type of Simulation Program with Integrated Circuit Emphasis (SPICE) demonstrating its potential for more efficient real-time data retrieval applications.

Implementation of High-Speed Serial I/O using Xilinx Tools in FPGA

The I/O (Input Output) module conveys the information between I/O device and processor. I/O devices are majorly of two types: Parallel I/O and Serial I/O. Parallel I/O performs multiple I/O operations simultaneously. Due to this speed and higher bandwidths are achieved, but the usage of parallel I/O devices is decreasing as time progresses because it involves complex design due to the usage of multiple wires for the transmission hence only limited to usage in shorter distances. It also uses a greater number of pins compared to serial I/O for the same number of data bits which makes its usage problematic in higher level devices. Serial I/O transmits individual data bits sequentially. It uses lesser number of lines for data transmission thereby reducing the design complexity. Since, the data transmission is sequential the signal delay increases. Thus, this project aims to develop a protocol which achieves High Speed Serial I/O which helps to increase the data rate from Mbps to Gbps, decrease the design complexity, to design hardware using fewer number of pins on PCB and reduce signal delay to maximum extent possible

Properties Investigation of Self-Dual Combinational Devices with Calculation Control Based on Hamming Codes

A new approach to the synthesis of self-checking devices is considered, based on the control of calculations in testing objects using Hamming codes, the check bits of which are described by self-dual functions. In this case, the structure operates in a pulsed mode, which is actually based on the introduction of temporal redundancy when building a self-checking device. This, unfortunately, leads to some decrease in performance, however, it significantly improves the characteristics of controllability, which is especially important for devices and systems of critical use, the input data for which does not change so often. A brief review of methods for constructing built-in control circuits based on the self-duality property of calculated functions is given. The basic structures of the organization of built-in control circuits are given. The proposed ways of developing the theory of synthesis of built-in control circuits are based on checking whether or not the calculated functions belong to a class of self-dual Boolean functions. All possible values of the number of data bits for Hamming codes have been established. They will have the property of the self-duality of functions describing control bits. En-coders of such Hamming codes will be self-dual devices. Since the functions of the check bits of Hamming codes are linear, in order for them to be self-dual, it is necessary that an odd number of arguments be used in each of them. It is proved that the number of bits of code words of Hamming codes with self-dual check functions is equal to n=3+4l, l∈N0. The results of the simulations self-dual devices with built-in control circuits along two diagnostic parameters in the Multisim environment are presented. A method is proposed for modification of the structure of calculation control along two diagnostic parameters, which allows to use any linear block code (not necessarily Hamming code). It is based on retrofitting the encoder with a device for converting functions into self-dual ones. In fact, this is a code modification device. It is proved that to obtain a modified Hamming code with self-dual control functions for n≠3+4l, l∈N0; cases, it is enough to add modulo M=2 the non-self-dual control function with the function of the high data bit.

Development of Hybrid Based Lossless Iris Image Compression Technique

The biometric iris recognition is the most popular method and is extended successfully in use, but unfortunately, a large number of data bits are exhausted when stored that implicitly affecting the transmission bandwidth and a compression solution is urgently required based on removing redundancy(s). In this paper a simple hybrid image compression scheme is proposed, it is based on using two techniques of polynomial coding and Fourier transform coding to efficiently encoded lossless. The test results of the suggested method showed that improved of compression performance is achieved with an identically based reconstruction image.

An Animated GIF Steganography Using Variable Block Partition Scheme

The paper presents a novel Graphics Interchange Format (GIF) Steganography system. The algorithm uses an animated (GIF) file format video to apply on, a secured and variable image partition scheme for data embedding. The secret data could be any character text, any image, an audio file, or a video file; that is converted in the form of bits. The proposed method uses a variable partition scheme structure for data embedding in the (GIF) file format video. The algorithm estimates the capacity of the cover (GIF) image frames to embed data bits. Our method built variable partition blocks in an empty frame separately and incorporate it with randomly selected (GIF) frames. This way the (GIF) frame is divided into variable block same as in the empty frame. Then algorithm embeds secret data on appropriate pixel of the (GIF) frame. Each selected partition block for data embedding, can store a different number of data bits based on block size. Intruders could never come to know exact position of the secrete data in this stego frame. All the (GIF) frames are rebuild to make animated stego (GIF) video. The performance of the proposed (GIF) algorithm has experimented and evaluated based on different input parameters, like Mean Square Error (MSE) and Peak Signal-to-Noise Ratio (PSNR) values. The results are compared with some existing methods and found that our method has promising results.

Perfect Trees: Designing Energy-Optimal Symmetric Encryption Primitives

Energy efficiency is critical in battery-driven devices, and designing energyoptimal symmetric-key ciphers is one of the goals for the use of ciphers in such environments. In the paper by Banik et al. (IACR ToSC 2018), stream ciphers were identified as ideal candidates for low-energy solutions. One of the main conclusions of this paper was that Trivium, when implemented in an unrolled fashion, was by far the most energy-efficient way of encrypting larger quantity of data. In fact, it was shown that as soon as the number of databits to be encrypted exceeded 320 bits, Trivium consumed the least amount of energy on STM 90 nm ASIC circuits and outperformed the Midori family of block ciphers even in the least energy hungry ECB mode (Midori was designed specifically for energy efficiency).In this work, we devise the first heuristic energy model in the realm of stream ciphers that links the underlying algebraic topology of the state update function to the consumptive behaviour. The model is then used to derive a metric that exhibits a heavy negative correlation with the energy consumption of a broad range of stream cipher architectures, i.e., the families of Trivium-like, Grain-like and Subterranean-like constructions. We demonstrate that this correlation is especially pronounced for Trivium-like ciphers which leads us to establish a link between the energy consumption and the security guarantees that makes it possible to find several alternative energy-optimal versions of Trivium that meet the requirements but consume less energy. We present two such designs Trivium-LE(F) and Trivium-LE(S) that consume around 15% and 25% less energy respectively making them the to date most energy-efficient encryption primitives. They inherit the same security level as Trivium, i.e., 80-bit security. We further present Triad-LE as an energy-efficient variant satisfying a higher security level. The simplicity and wide applicability of our model has direct consequences for the conception of future hardware-targeted stream ciphers as for the first time it is possible to optimize for energy during the design phase. Moreover, we extend the reach of our model beyond plain encryption primitives and propose a novel energy-efficient message authentication code Trivium-LE-MAC.

Quant-PIM: An Energy-Efficient Processing-in-Memory Accelerator for Layerwise Quantized Neural Networks

Layerwise quantized neural networks (QNNs), which adopt different precisions for weights or activations in a layerwise manner, have emerged as a promising approach for embedded systems. The layerwise QNNs deploy only required number of data bits for the computation (e.g., convolution of weights and activations), which in turn reduces computation energy compared to the conventional QNNs. However, the layerwise QNNs still cause a large amount of energy in the conventional memory systems, since memory accesses are not optimized for the required precision of each layer. To address this problem, we propose <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Quant-PIM</i> , an energy-efficient processing-in-memory (PIM) accelerator for layerwise QNNs. Quant-PIM selectively reads only required data bits within a data word depending on the precision, by deploying the modified I/O gating logics in a 3-D stacked memory. Thus, Quant-PIM significantly reduces energy consumption for memory accesses. In addition, Quant-PIM improves the performance of layerwise QNNs. When the required precision is half of the weight (or activation) size or less, Quant-PIM reads two data blocks in a single read operation by exploiting the saved memory bandwidth from the selective memory access, thus providing higher compute-throughput. Our simulation results show that Quant-PIM reduces system energy by 39.1%~50.4% compared to the PIM system with 16-bit quantized precision, without accuracy loss.

Research on parallel principal component analysis based on ternary optical computer

Principal component analysis (PCA) is a widely used algorithm in the field of artificial intelligence and statistical analysis. When dealing with a large number of high-dimensional data, the traditional PCA algorithm has some shortcomings, such as slow processing speed, high power consumption, low computational efficiency. By taking advantage of several characteristics which include large number of data bits, easy-expansion of data bits, and parallel computing in ternary optical computer (TOC), the implementation scheme of parallel PCA algorithm is studied. Through the analysis of the traditional PCA algorithm, the parallel parts are found out and parallel design is carried out. Then, the elaborate implementation flow of the algorithm is given, and the clock cycle and hardware resources of the algorithm are also analyzed. Finally, the validity of the parallel scheme is proved by experiments. Compared with the traditional PCA algorithm, the PCA algorithm based on TOC has better time performance, operational efficiency, and gives full play to the advantage of ternary optical computer in processing complex computation.

Highly Sensitive Implementation of Logic Gates with a Nonlinear Nanomechanical Resonator

We introduce a theoretical concept of logic gates for sequenced data that contain a large number of data bits to be computed using a nonlinear nanomechanical resonator. Resonantly driven nanomechanical modes display the bistability of forced vibrations. Near the cusp point on the bifurcation curve, even a small change in driving force can lead to switching between the vibrational states with significantly different amplitudes. This enables a highly sensitive implementation of logic gates, including and, or, and xor gates. The underlying principles are simple and generic, suggesting that our method is applicable not only to nanomechanical systems but also to a wide variety of bistable physical, chemical, and biological systems.

SCMA System Design With Index Modulation via Codebook Assignment

Sparse code multiple access (SCMA) is a promising non-orthogonal multiple access (NOMA) scheme for massive machine-type communications for 5G-and-beyond communication systems. Innovative use of orthogonal frequency division multiplexing with index modulation (OFDM-IM) takes advantage of using tone indices in data transmission. In this study, we propose a novel multiplexing and multiple access scheme, namely SCMA based on OFDM-IM (SCMA-IM). SCMA-IM method can be implemented in uplink NOMA systems in an efficient way with similar computational complexity as SCMA. In this method constellation differences and diversity are obtained via SCMA codebooks (CBs) and the employment of CBs is transferred to index modulation (IM). Performance improvement is achieved via CBs so that the number of data bits carried by indices increases more than one bit with different constellations, and also with the number of CBs assigned. In order to determine the indices used in IM, the receiver structure is simplified by the message passing algorithm and log-likelihood ratio detection process used in SCMA receivers without indexing the receiver. Thus, a new NOMA scheme is obtained by coding with IM. Bit error rate performance of the system is studied for 150% and 200% overloading factors.

Implementation of wavelet transform on optical computer

As one of the most useful mathematical analysis method, discrete wavelet transform (DWT) has been widely used in many fields such as signal analysis, image processing and so on. However because of its tremendous computational complexity, the application of DWT has been greatly affected. In consideration that DWT can be high efficiently implemented in parallel by utilizing huge number of data bits of optical computer, it is meaningful and important to study on how to implement DWT on ternary optical computer (TOC). To simplify the application of DWT on TOC, a new implementation strategy of DWT based on TOC is put forward. Fully considered the relations between the operands and the resources of TOC, the mechanisms and details about the implementation of carry-free DWT are discussed. With the implementation strategy, users can easily accomplish DWT by giving the needed DWT application parameters without needing to know the details of TOC and the intermediate process of DWT calculation. Experiments show that the implementation strategy is correct, it can effectively implement and much simplify the application of DWT on TOC. Meanwhile, it can automatically generate all the needed intermediate information and ensure the whole application process of DWT be transparent to users.

On Minimizing Analog Variation Errors to Resolve the Scalability Issue of ReRAM-Based Crossbar Accelerators

Crossbar accelerators with a resistive random-access memory (ReRAM) are a promising solution for accelerating neural network applications. The advantages of achieving high computation throughput per watt make ReRAM-based crossbar accelerators become a potential solution for accelerating inference operations in the Internet of Things and edge devices. Due to the analog variation errors, the launched ReRAM-based crossbar accelerators can only perform well when each ReRAM cell is used to represent a limited number of data bits. To make such ReRAM-based crossbar accelerators applicable in wide application scenarios, several proposed researches target at binary neural networks and focus on the chip designs in relieving the implementation challenges on computation accuracy for realizing single-bit ReRAM-based crossbar accelerators. Even though several small-sized ReRAM-based crossbar accelerators are announced, the scalability issue hinders ReRAM-based crossbar accelerators from being scaled up. That is, when there are more and more wordline in an ReRAM-based crossbar accelerator, the analog variation error is amplified and thus seriously degrades the computation accuracy. In this work, we propose an adaptive data manipulation strategy to substantially reduce analog variation errors so as to fill up the gap on scaling up the ReRAM-based crossbar accelerators. In particular, a weightrounding design is proposed to manipulate data to minimize overlapping variation so that the number of wordlines can be scaled up. In addition, an input subcycling design is proposed to further trade tolerable errors with neural networks' execution time. Moreover, a bitline redundant design is proposed to trade acceptable space overhead for eliminating the analog variation errors. The emulation experiments show that the proposed adaptive data manipulation strategy can improve the accuracy in running MNIST and CIFAR-10 by 1.3× and 2.6× with nearly no management penalty and hardware cost. The experimental results also show the close-to-ideal-case accuracy by substantially reducing analog variation errors.

Implementation of Text Compression using Adaptive Shannon-Fano Algorithm

This study aims to implement the Shannon-fano Adaptive data compression algorithm on characters as input data. This study also investigates the data compression ratio, which is the ratio between the number of data bits before and after compression. The resulting program is tested by using black-box testing, measuring the number of character variants and the number of types of characters to the compression ratio, and testing the objective truth with the Mean Square Error (MSE) method. The description of the characteristics of the application made is done by processing data in the form of a collection of characters that have different types of characters, variants, and the number of characters. This research presents algorithm that support the steps of making adaptive Shannon-fano compression applications. The length of the character determines the variant value, compression ratio, and the number of input character types. Based on the results of test results, no error occurs according to the comparison of the original text input and the decompression results. A higher appearance frequency of a character causes a greater compression ratio of the resulting file; the analysis shows that a higher number of types of input characters causes a lower compression ratio, which proves that the proposed method in real-time data compression improves the effectiveness and efficiency of the compression process.

Resource allocation in downlink SWIPT-based cooperative NOMA systems

This paper considers a downlink multi-carrier cooperative non-orthogonal multiple access (NOMA) transmission, where no direct link exists between the far user and the base station (BS), and the communication between them only relies on the assist of the near user. Firstly, the BS sends a superimposed signal of the far and the near user to the near user, and then the near user adopts simultaneous wireless information and power transfer (SWIPT) to split the received superimposed signal into two portions for energy harvesting and information decoding respectively. Afterwards, the near user forwards the signal of the far user by utilizing the harvested energy. A minimum data is required to ensure the quality of service (QoS) of the far user. We jointly optimize power allocation, subcarrier allocation, time allocation, the power allocation (PA) coefficient and the power splitting (PS) ratio to maximize the number of data bits received at the near user under the energy causality constraint, the minimum data constraint and the transmission power constraint. The block-coordinate descent method and the Lagrange duality method are used to obtain a suboptimal solution of this optimization problem. In the final simulation results, the superiority of the proposed NOMA scheme is confirmed compared with the benchmark NOMA schemes and the orthogonal multiple access (OMA) scheme.

The application of SJ-MSD adder to mean value filtering processing

Based on the transformations of SJ-MSD (modified-signed digit) addition and the principle of SJ-MSD adder, the application of SJ-MSD adder of TOC to mean value filtering (ternary optical computer) is introduced. The realization of mean filtering processing is presented by reconfiguring SJ-MSD adders on TOP (ternary optical processor) in detail. Experiments show that the mean filter processing in TOC can be carried out successfully with a multiple of SJ-MSD parallel adders with large number of data bits. It also shows a great promise and advantages for the application of TOC in digital image processing and other respects.

Random-Access NOMA in URLL Energy-Harvesting IoT Networks With Short Packet and Diversity Transmissions

Non-orthogonal multiple-access (NOMA) has recently been proposed to improve throughput and spectrum-efficiency of 5G cellular networks and beyond. It is also a key enabler for ultra-reliable and low-latency (URLL) communications. Moreover, the Internet-of-Things (IoT) paradigm has emerged to practically provide massive connectivity for smart devices and systems, which entails spectrum- and energy-efficient transmission schemes. To this aim, NOMA and energy-harvesting (EH) solutions have been put forth to address such demands, making the combination of such technologies inevitable in NOMA-based URLL-EH-IoT networks. On the other hand, random-access (RA) techniques are the key solution to enable massive URLL-EH-IoT networks, since they reduce signaling overhead, packet latency, and energy consumption when massive numbers of clustered IoT devices with sporadic traffic behavior are considered. In this paper, uplink RA-NOMA in URLL-EH-IoT networks with short packet and diversity transmissions is studied and analyzed. Network metrics—such as average packet latency, reliability, and GoodPut—are derived for the RA-NOMA scenario and compared with its RA-OMA counterpart to explore the advantages of RA-NOMA over RA-OMA. Moreover, the analytical derivations have been validated and shown to coincide with the simulation results. Furthermore, the effect of the transmission diversity and number of data bits per blocklength on the different network metrics are extensively evaluated. Lastly, the analytical derivations are utilized to find the optimum values of the IoT nodes’ transmit power, number of packet replicas, and number of transmitted data bits per blocklength, such that the maximum sum-GoodPut of a RA-NOMA IoT cluster is achieved, subject to URLL constraints.

Microwave performance of flexo-printed chipless RFID tags

The chipless RFID tag is considered as a potential candidate to replace the expensive chip-based tags due to the possibility of high volume tag production by low-cost printing processes. In this paper, we report on the microwave performance of chipless tags printed by a benchtop flexographic printer using low-cost water-based silver ink obtained from NovaCentrix. The designed chipless RFID tags were based on the frequency-domain ‘Data Encoding’ due to its merit to encode a higher number of data bits compared to other domains of data encoding. The printed silver ink tracks were optimized for best printer settings in terms of the adjustments of the gap between the rollers, print speed and ink volume. The dependence of the RCS response on the actual tag area to be covered in metal ink, relative to the designed tag area, was investigated and a way to obtain an increased RCS response was studied. It was found that printing at least two copies of resonators can enhance the detected RCS response for any specific tag configuration. Tags printed on Mylar PET film gave the best RCS performance compared to tags printed on thermal paper and PVC film.

A Carry-Free Multiplication Implementation Method

Delay caused by carry propagation is an unfavourable issue that much affects the efficiency of numerical computing in computer system. And the more data bits of the operands, the worse the delay. As data bits of the operands in optical computer can be huge because of the high information capability of light, this makes carry delay be very serious. As multiplication is one of the most important and popular calculations and many multiplications can be carried out in parallel by utilizing huge number of data bits of optical computer, study on how to reduce or even mitigate carry delay in multiplication is very important. To improve the multiplication efficiency, a new carry free method to design and implement multiplication based on Ternary Optical Computer (TOC) is put forward. Fully considering the relations between the operands based on modified signed-digit (MSD) number system, a parallel mulitplication implemeation strategy together with its resource allocation method is presented. The experimental results show that the proposed strategy is correct. It exerts the advantages of optical computing and ensures that no carry delay is introduced in the process of multiplication which much improves the efficiency of optical multiplication applications.

Steganography via MIDI Files by Adjusting Velocities of Musical Note Sequences With Monotonically Non-Increasing or Non-Decreasing Pitches

Data hiding techniques for steganography, which embed secret data in multimedia imperceptibly, are useful for protecting information security. By taking advantage of the popularity of MIDI files on the Internet, a new data hiding method via MIDI files is proposed, which modifies the velocities of musical note sequences to embed secret data. Initially, musical note sequences with monotonic pitches, each consisting of at least three consecutive notes with pitches either entirely non-decreasing or entirely non-increasing, are found from an input MIDI file. Next, for each of such musical note sequences, a reference velocity is generated for each non-end note in the sequence by a linear interpolation scheme. Then, a number of data bits are embedded into each non-end note by adding the decimal value of the bits to or subtracting the value from the corresponding reference velocity value to yield a new velocity for the note. The new velocity value does not differ much from the original one and fits the velocity trend in the musical note sequence, so that the resulting stego-MIDI file does not yield abnormal note strengths and the musical expression is kept. Moreover, a melody humanization scheme is proposed for modifying the velocity values in strength-invariant MIDI channels to create data embeddability without producing unreasonable melodies. The original MIDI file size is also kept unchanged after data embedding, avoiding attracting attentions from hackers. Experimental results show the feasibility of the proposed method. Also, a comparison with five other methods show that the method has the merit of reducing the resulting melody distortion or file-size change while yielding a reasonable secret-bit embedding rate.